/*
* ======== Init_Clock ========
*/
VOID Init_Clock (VOID)
{
//Initialization of clock module
if (USB_PLL_XT == 2){
#if defined (__MSP430F552x) || defined (__MSP430F550x)
P5SEL |= 0x0C; //enable XT2 pins for F5529
#elif defined (__MSP430F563x_F663x)
P7SEL |= 0x0C;
#endif
//use REFO for FLL and ACLK
UCSCTL3 = (UCSCTL3 & ~(SELREF_7)) | (SELREF__REFOCLK);
UCSCTL4 = (UCSCTL4 & ~(SELA_7)) | (SELA__REFOCLK);
//MCLK will be driven by the FLL (not by XT2), referenced to the REFO
Init_FLL_Settle(USB_MCLK_FREQ / 1000, USB_MCLK_FREQ / 32768); //Start the FLL, at the freq indicated by the config
//constant USB_MCLK_FREQ
XT2_Start(XT2DRIVE_0); //Start the "USB crystal"
}
else {
#if defined (__MSP430F552x) || defined (__MSP430F550x)
P5SEL |= 0x10; //enable XT1 pins
#endif
//Use the REFO oscillator to source the FLL and ACLK
UCSCTL3 = SELREF__REFOCLK;
UCSCTL4 = (UCSCTL4 & ~(SELA_7)) | (SELA__REFOCLK);
//MCLK will be driven by the FLL (not by XT2), referenced to the REFO
Init_FLL_Settle(USB_MCLK_FREQ / 1000, USB_MCLK_FREQ / 32768); //set FLL (DCOCLK)
XT1_Start(XT1DRIVE_0); //Start the "USB crystal"
}
}
/***************************************************************************//**
* @brief Initializes USB clock
* @param none
* @return none
******************************************************************************/
void ClockUSB(void)
{
if (USB_PLL_XT == 2)
{
P5SEL |= 0x0C; // Enable the XT2 pins. Without this, the xtal pins default to being I/O's.
// Use the REFO oscillator to source the FLL and ACLK
UCSCTL3 = (UCSCTL3 & ~(SELREF_7)) | (SELREF__REFOCLK);
UCSCTL4 = (UCSCTL4 & ~(SELA_7)) | (SELA__REFOCLK);
// MCLK will be driven by the FLL (not by XT2), referenced to the REFO
SFRIE1 &= ~OFIE;
Init_FLL_Settle(USB_MCLK_FREQ/1000, USB_MCLK_FREQ/32768); // Start the FLL, at the freq indicated by the config constant USB_MCLK_FREQ
XT2_Start(XT2DRIVE_0); // Start the "USB crystal"
SFRIE1 |= OFIE;
}
else
{
P5SEL |= 0x10; // Enable the XT1 pins. Without this, the xtal pins default to being I/O's.
// Use the REFO oscillator to source the FLL and ACLK
UCSCTL3 = SELREF__REFOCLK;
UCSCTL4 = (UCSCTL4 & ~(SELA_7)) | (SELA__REFOCLK);
SFRIE1 &= ~OFIE;
// MCLK will be driven by the FLL (not by XT2), referenced to the REFO
Init_FLL_Settle(USB_MCLK_FREQ/1000, USB_MCLK_FREQ/32768); // set FLL (DCOCLK)
XT1_Start(XT1DRIVE_0); // Start the "USB crystal"
SFRIE1 |= OFIE;
}
}
BYTE USB_enable()
{
volatile unsigned int i;
volatile unsigned int j = 0;
if (!(USBPWRCTL & USBBGVBV)) // check USB Bandgap and VBUS valid
{
return kUSB_generalError;
}
if ((USBCNF & USB_EN) &&
(USBPLLCTL & UPLLEN))
{
return kUSB_succeed; // exit if PLL is already enalbed
}
USBKEYPID = 0x9628; // set KEY and PID to 0x9628 -> access to configuration registers enabled
XT2_Start(XT2DRIVE_3);
USBPLLDIVB = USB_XT_FREQ; // Settings desired frequency
if (USB_PLL_XT == 2)
{
USBPLLCTL = UPCS0 + UPFDEN + UPLLEN;// Select XT2 as Ref / Select PLL for USB / Discrim. on, enable PLL
}
else
{
USBPLLCTL = UPFDEN + UPLLEN; // Select XT1 as Ref / Select PLL for USB / Discrim. on, enable PLL
}
//Wait some time till PLL is settled
do
{
USBPLLIR = 0x0000; // make sure no interrupts can occur on PLL-module
#ifdef __MSP430F6638
//wait 1 ms till enable USB
for (i =0; i < USB_MCLK_FREQ/1000*1/10; i++);
#else
//wait 1/2 ms till enable USB
for (i =0; i < USB_MCLK_FREQ/1000* 1/2 /10; i++);
#endif
if (j++ > 10)
{
USBKEYPID = 0x9600; // access to configuration registers disabled
return kUSB_generalError;
}
}while (USBPLLIR != 0);
USBCNF |= USB_EN; // enable USB module
USBKEYPID = 0x9600; // access to configuration registers disabled
return kUSB_succeed;
}
void init_clock(void) {
// enable XT2 pins for F5529
P5SEL |= 0x0C;
UCSCTL3 = (UCSCTL3 & ~(SELREF_7)) | (SELREF__REFOCLK);
UCSCTL4 = (UCSCTL4 & ~(SELA_7)) | (SELA__REFOCLK);
//Start the USB crystal (XT2)
XT2_Start(XT2DRIVE_0);
// use XT2 for FLL source
UCSCTL3 = SELREF__XT2CLK;
// use XT1 for ACLK, XT2 for SMCLK and MCLK
UCSCTL4 = SELA__XT1CLK | SELS__XT2CLK | SELM__XT2CLK;
//!@todo stuck here
//Init_FLL_Settle(8000, 4);
P1DIR |= BIT0;
P1OUT |= BIT0;
}
VOID Init_Clock(VOID)
{
# if defined (__MSP430F563x_F663x)
while(BAKCTL & LOCKIO) // Unlock XT1 pins for operation
BAKCTL &= ~(LOCKIO); // enable XT1 pins
// Workaround for USB7
UCSCTL6 &= ~XT1OFF;
# endif
//Initialization of clock module
if (USB_PLL_XT == 2)
{
# if defined (__MSP430F552x) || defined (__MSP430F550x)
P5SEL |= 0x0C; // enable XT2 pins for F5529
# elif defined (__MSP430F563x_F663x)
P7SEL |= 0x0C;
# endif
// use REFO for FLL and ACLK
UCSCTL3 = (UCSCTL3 & ~(SELREF_7)) | (SELREF__REFOCLK);
UCSCTL4 = (UCSCTL4 & ~(SELA_7)) | (SELA__REFOCLK);
Init_FLL(USB_MCLK_FREQ/1000, USB_MCLK_FREQ/32768); // set FLL (DCOCLK)
XT2_Start(XT2DRIVE_3);
}
else
{
# if defined (__MSP430F552x) || defined (__MSP430F550x)
P5SEL |= 0x10; // enable XT1 pins
# endif
UCSCTL3 = SELREF__REFOCLK; // run FLL mit REF_O clock
UCSCTL4 = (UCSCTL4 & ~(SELA_7)) | (SELA__REFOCLK); // set ACLK = REFO
Init_FLL(USB_MCLK_FREQ/1000, USB_MCLK_FREQ/32768); // set FLL (DCOCLK)
XT1_Start(XT1DRIVE_3);
}
// SFRIE1 |= OFIFG; // Enable OscFault ISR
}