/** * * API to get bus speed supported by card. * * * @param InstancePtr is a pointer to the XSdPs instance. * @param ReadBuff - buffer to store function group support data * returned by card. * * @return * - XST_SUCCESS if successful. * - XST_FAILURE if fail. * * @note None. * ******************************************************************************/ int XSdPs_Get_BusSpeed(XSdPs *InstancePtr, u8 *ReadBuff) { u32 Status = 0; u32 StatusReg = 0x0; u32 Arg = 0; u16 BlkCnt; u16 BlkSize; int LoopCnt; Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); for (LoopCnt = 0; LoopCnt < 64; LoopCnt++) { ReadBuff[LoopCnt] = 0; } BlkCnt = XSDPS_SWITCH_CMD_BLKCNT; BlkSize = XSDPS_SWITCH_CMD_BLKSIZE; BlkSize &= XSDPS_BLK_SIZE_MASK; XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_BLK_SIZE_OFFSET, BlkSize); XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, ReadBuff); XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_XFER_MODE_OFFSET, XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK); Arg = XSDPS_SWITCH_CMD_HS_GET; Xil_DCacheInvalidateRange(ReadBuff, 64); Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 1); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } /* * Check for transfer complete * Polling for response for now */ do { StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, XSDPS_NORM_INTR_STS_OFFSET); if (StatusReg & XSDPS_INTR_ERR_MASK) { /* Write to clear error bits */ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_ERR_INTR_STS_OFFSET, XSDPS_ERROR_INTR_ALL_MASK); Status = XST_FAILURE; goto RETURN_PATH; } } while ((StatusReg & XSDPS_INTR_TC_MASK) == 0); /* Write to clear bit */ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK); Status = XSdPs_ReadReg(InstancePtr->Config.BaseAddress, XSDPS_RESP0_OFFSET); Status = XST_SUCCESS; RETURN_PATH: return Status; }
/** * * API to get bus width support by card. * * * @param InstancePtr is a pointer to the XSdPs instance. * @param SCR - buffer to store SCR register returned by card. * * @return * - XST_SUCCESS if successful. * - XST_FAILURE if fail. * * @note None. * ******************************************************************************/ int XSdPs_Get_BusWidth(XSdPs *InstancePtr, u8 *SCR) { u32 Status = 0; u32 StatusReg = 0x0; u16 BlkCnt; u16 BlkSize; int LoopCnt; Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); for (LoopCnt = 0; LoopCnt < 8; LoopCnt++) { SCR[LoopCnt] = 0; } /* Send block write command */ Status = XSdPs_CmdTransfer(InstancePtr, CMD55, InstancePtr->RelCardAddr, 0); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } BlkCnt = XSDPS_SCR_BLKCNT; BlkSize = XSDPS_SCR_BLKSIZE; /* Set block size to the value passed */ BlkSize &= XSDPS_BLK_SIZE_MASK; XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_BLK_SIZE_OFFSET, BlkSize); XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, SCR); XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_XFER_MODE_OFFSET, XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK); Xil_DCacheInvalidateRange(SCR, 8); Status = XSdPs_CmdTransfer(InstancePtr, ACMD51, 0, BlkCnt); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } /* * Check for transfer complete * Polling for response for now */ do { StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, XSDPS_NORM_INTR_STS_OFFSET); if (StatusReg & XSDPS_INTR_ERR_MASK) { /* Write to clear error bits */ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_ERR_INTR_STS_OFFSET, XSDPS_ERROR_INTR_ALL_MASK); Status = XST_FAILURE; goto RETURN_PATH; } } while ((StatusReg & XSDPS_INTR_TC_MASK) == 0); /* Write to clear bit */ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK); Status = XSdPs_ReadReg(InstancePtr->Config.BaseAddress, XSDPS_RESP0_OFFSET); Status = XST_SUCCESS; RETURN_PATH: return Status; }
void emacps_recv_handler(void *arg) { struct pbuf *p; unsigned irq_status, i; XEmacPs_Bd *rxbdset, *CurBdPtr; struct xemac_s *xemac; xemacpsif_s *xemacpsif; XEmacPs_BdRing *rxring; volatile int bd_processed; int rx_bytes, k; unsigned int BdIndex; xemac = (struct xemac_s *)(arg); xemacpsif = (xemacpsif_s *)(xemac->state); rxring = &XEmacPs_GetRxRing(&xemacpsif->emacps); #ifdef OS_IS_FREERTOS xInsideISR++; #endif /* * If Reception done interrupt is asserted, call RX call back function * to handle the processed BDs and then raise the according flag. */ while(1) { bd_processed = XEmacPs_BdRingFromHwRx(rxring, XLWIP_CONFIG_N_RX_DESC, &rxbdset); if (bd_processed <= 0) { #ifdef OS_IS_FREERTOS xInsideISR--; #endif return; } for (k = 0, CurBdPtr=rxbdset; k < bd_processed; k++) { BdIndex = XEMACPS_BD_TO_INDEX(rxring, CurBdPtr); p = (struct pbuf *)rx_pbufs_storage[BdIndex]; /* * Adjust the buffer size to the actual number of bytes received. */ rx_bytes = XEmacPs_BdGetLength(CurBdPtr); pbuf_realloc(p, rx_bytes); Xil_DCacheInvalidateRange((unsigned int)p->payload, (unsigned)XEMACPS_MAX_FRAME_SIZE); /* store it in the receive queue, * where it'll be processed by a different handler */ if (pq_enqueue(xemacpsif->recv_q, (void*)p) < 0) { #if LINK_STATS lwip_stats.link.memerr++; lwip_stats.link.drop++; #endif pbuf_free(p); } else { #if !NO_SYS sys_sem_signal(&xemac->sem_rx_data_available); #endif } CurBdPtr = XEmacPs_BdRingNext( rxring, CurBdPtr); } /* free up the BD's */ XEmacPs_BdRingFree(rxring, bd_processed, rxbdset); _setup_rx_bds(rxring); } return; }
/** * This function performs SD read in polled mode. * * @param InstancePtr is a pointer to the instance to be worked on. * @param Arg is the address passed by the user that is to be sent as * argument along with the command. * @param BlkCnt - Block count passed by the user. * @param Buff - Pointer to the data buffer for a DMA transfer. * * @return * - XST_SUCCESS if initialization was successful * - XST_FAILURE if failure - could be because another transfer * is in progress or command or data inhibit is set * ******************************************************************************/ int XSdPs_ReadPolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, u8 *Buff) { u32 Status; u32 PresentStateReg; u32 StatusReg; /* * Check status to ensure card is initialized */ PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress, XSDPS_PRES_STATE_OFFSET); if ((PresentStateReg & XSDPS_PSR_CARD_INSRT_MASK) == 0x0) { Status = XST_FAILURE; goto RETURN_PATH; } /* * Set block size to 512 if not already set */ if( XSdPs_ReadReg(InstancePtr->Config.BaseAddress, XSDPS_BLK_SIZE_OFFSET) != XSDPS_BLK_SIZE_512_MASK ) { Status = XSdPs_SetBlkSize(InstancePtr, XSDPS_BLK_SIZE_512_MASK); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } } XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, Buff); XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_XFER_MODE_OFFSET, XSDPS_TM_AUTO_CMD12_EN_MASK | XSDPS_TM_BLK_CNT_EN_MASK | XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK | XSDPS_TM_MUL_SIN_BLK_SEL_MASK); Xil_DCacheInvalidateRange(Buff, BlkCnt * XSDPS_BLK_SIZE_512_MASK); /* * Send block read command */ Status = XSdPs_CmdTransfer(InstancePtr, CMD18, Arg, BlkCnt); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } /* * Check for transfer complete */ do { StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, XSDPS_NORM_INTR_STS_OFFSET); if (StatusReg & XSDPS_INTR_ERR_MASK) { /* * Write to clear error bits */ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_ERR_INTR_STS_OFFSET, XSDPS_ERROR_INTR_ALL_MASK); Status = XST_FAILURE; goto RETURN_PATH; } } while((StatusReg & XSDPS_INTR_TC_MASK) == 0); /* * Write to clear bit */ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK); Status = XSdPs_ReadReg(InstancePtr->Config.BaseAddress, XSDPS_RESP0_OFFSET); Status = XST_SUCCESS; RETURN_PATH: return Status; }
static void hw_op_matrix_alg_post_op(const Hw_Op *self) { // Invalidate data destination buffer data cache to force correct PS read Xil_DCacheInvalidateRange(self->args[2], MATRIX_WIDTH * MATRIX_WIDTH * sizeof(data_t)); }