void vHardwareUseMultiVectoredInterrupts( void )
{
/* Enable multi-vector interrupts. */
_CP0_BIS_CAUSE( 0x00800000U );
INTCONSET = _INTCON_MVEC_MASK;
__builtin_enable_interrupts();
}
void sys_cpu_en_timer(uint32_t counts, uint8_t ien)
{
/* Disable Counter by setting DC bit to 1 in CP0.Cause */
_CP0_BIS_CAUSE(_CP0_CAUSE_DC_MASK);
_CP0_SET_COUNT(counts);
if (ien) {
jtvic_en_source(MEC14xx_GIRQ24_ID, 0, 0);
} else {
jtvic_dis_clr_source(MEC14xx_GIRQ24_ID, 0, 1);
}
/* Enable Counter */
_CP0_BIC_CAUSE(_CP0_CAUSE_DC_MASK);
}
void vPortIncrementTick( void )
{
unsigned portBASE_TYPE uxSavedStatus;
uxSavedStatus = uxPortSetInterruptMaskFromISR();
{
if( xTaskIncrementTick() != pdFALSE )
{
/* Pend a context switch. */
_CP0_BIS_CAUSE( portCORE_SW_0 );
}
}
vPortClearInterruptMaskFromISR( uxSavedStatus );
/* Clear timer 1 interrupt. */
IFS0CLR = _IFS0_T1IF_MASK;
}
void vPortIncrementTick( void )
{
unsigned portBASE_TYPE uxSavedStatus;
uxSavedStatus = uxPortSetInterruptMaskFromISR();
vTaskIncrementTick();
vPortClearInterruptMaskFromISR( uxSavedStatus );
/* If we are using the preemptive scheduler then we might want to select
a different task to execute. */
#if configUSE_PREEMPTION == 1
_CP0_BIS_CAUSE( portCORE_SW_0 );
#endif /* configUSE_PREEMPTION */
/* Clear timer 1 interrupt. */
IFS0CLR = _IFS0_T1IF_MASK;
}
void vPortIncrementTick( void )
{
UBaseType_t uxSavedStatus;
uxSavedStatus = uxPortSetInterruptMaskFromISR();
{
if( xTaskIncrementTick() != pdFALSE )
{
/* Pend a context switch. */
_CP0_BIS_CAUSE( portCORE_SW_0 );
}
}
vPortClearInterruptMaskFromISR( uxSavedStatus );
/* Look for the ISR stack getting near or past its limit. */
portCHECK_ISR_STACK();
/* Clear timer interrupt. */
configCLEAR_TICK_TIMER_INTERRUPT();
}
void systemInit(void)
{
//Execute system unlock sequence
SYSKEY = 0xAA996655;
SYSKEY = 0x556699AA;
//Check PBDIVRDY bit
while(!(PB2DIV & _PB2DIV_PBDIVRDY_MASK));
//Configure PBCLK2 clock divisor (SYSCLK / 5);
PB2DIV = _PB2DIV_ON_MASK | 4;
//Check PBDIVRDY bit
while(!(PB3DIV & _PB3DIV_PBDIVRDY_MASK));
//Configure PBCLK3 clock divisor (SYSCLK / 5);
PB3DIV = _PB3DIV_ON_MASK | 4;
//Check PBDIVRDY bit
while(!(PB4DIV & _PB4DIV_PBDIVRDY_MASK));
//Configure PBCLK4 clock divisor (SYSCLK / 1);
PB4DIV = _PB4DIV_ON_MASK | 0;
//Check PBDIVRDY bit
while(!(PB5DIV & _PB5DIV_PBDIVRDY_MASK));
//Configure PBCLK5 clock divisor (SYSCLK / 2);
PB5DIV = _PB5DIV_ON_MASK | 1;
//Relock the SYSKEY
SYSKEY = 0;
//Disable interrupts
__builtin_disable_interrupts();
//Set IV
_CP0_BIS_CAUSE(_CP0_CAUSE_IV_MASK);
//Enable multi-vectored mode
INTCONSET = _INTCON_MVEC_MASK;
}
