C++ (Cpp) _DELAY Examples

Example #1

File: plf_misc.c Project: lijinlei/Kernel_BOOX60

void 
cyg_hal_plf_pci_cfg_write_byte (cyg_uint32 bus, cyg_uint32 devfn,
                                cyg_uint32 offset, cyg_uint8  data)
{
    cyg_uint32 config_dword, shift;

    HAL_WRITE_UINT32(CYGARC_REG_PCI_CFG_ADDR,
                     CYGARC_REG_PCI_CFG_ADDR_ENABLE |
                     (bus << CYGARC_REG_PCI_CFG_ADDR_BUSNO_shift) |
                     (devfn << CYGARC_REG_PCI_CFG_ADDR_FUNC_shift) |
                     (offset & ~3));
    HAL_WRITE_UINT32(CYGARC_REG_PCI_CFG_CMD, CYGARC_REG_PCI_CFG_CMD_RCFG);
    _DELAY();
    HAL_READ_UINT32(CYGARC_REG_PCI_CFG_DATA, config_dword);

    shift = (offset & 3) * 8;
    config_dword &= ~(0xff << shift);
    config_dword |= (data << shift);

    HAL_WRITE_UINT32(CYGARC_REG_PCI_CFG_ADDR,
                     CYGARC_REG_PCI_CFG_ADDR_ENABLE |
                     (bus << CYGARC_REG_PCI_CFG_ADDR_BUSNO_shift) |
                     (devfn << CYGARC_REG_PCI_CFG_ADDR_FUNC_shift) |
                     (offset & ~3));
    HAL_WRITE_UINT32(CYGARC_REG_PCI_CFG_DATA, config_dword);
    _DELAY();
    HAL_WRITE_UINT32(CYGARC_REG_PCI_CFG_CMD, CYGARC_REG_PCI_CFG_CMD_WCFG);
    _DELAY();
}

Example #2

File: plf_misc.c Project: lijinlei/Kernel_BOOX60

void
cyg_hal_plf_pci_cfg_write_dword (cyg_uint32 bus, cyg_uint32 devfn,
                                 cyg_uint32 offset, cyg_uint32 data)
{
    HAL_WRITE_UINT32(CYGARC_REG_PCI_CFG_ADDR,
                     CYGARC_REG_PCI_CFG_ADDR_ENABLE |
                     (bus << CYGARC_REG_PCI_CFG_ADDR_BUSNO_shift) |
                     (devfn << CYGARC_REG_PCI_CFG_ADDR_FUNC_shift) |
                     (offset));
    HAL_WRITE_UINT32(CYGARC_REG_PCI_CFG_DATA, data);
    _DELAY();
    HAL_WRITE_UINT32(CYGARC_REG_PCI_CFG_CMD, CYGARC_REG_PCI_CFG_CMD_WCFG);
    _DELAY();
}

Example #3

File: plf_misc.c Project: lijinlei/Kernel_BOOX60

//--------------------------------------------------------------------------
// Config space accessor functions
cyg_uint32
cyg_hal_plf_pci_cfg_read_dword (cyg_uint32 bus, cyg_uint32 devfn,
                                cyg_uint32 offset)
{
    cyg_uint32 config_data;

    HAL_WRITE_UINT32(CYGARC_REG_PCI_CFG_ADDR,
                     CYGARC_REG_PCI_CFG_ADDR_ENABLE |
                     (bus << CYGARC_REG_PCI_CFG_ADDR_BUSNO_shift) |
                     (devfn << CYGARC_REG_PCI_CFG_ADDR_FUNC_shift) |
                     (offset));
    HAL_WRITE_UINT32(CYGARC_REG_PCI_CFG_CMD, CYGARC_REG_PCI_CFG_CMD_RCFG);
    _DELAY();
    HAL_READ_UINT32(CYGARC_REG_PCI_CFG_DATA, config_data);

    return config_data;
}

Example #4

File: plf_misc.c Project: lijinlei/Kernel_BOOX60

cyg_uint8
cyg_hal_plf_pci_cfg_read_byte (cyg_uint32 bus, cyg_uint32 devfn, 
                               cyg_uint32 offset)
{
    cyg_uint32 config_dword;

    HAL_WRITE_UINT32(CYGARC_REG_PCI_CFG_ADDR,
                     CYGARC_REG_PCI_CFG_ADDR_ENABLE |
                     (bus << CYGARC_REG_PCI_CFG_ADDR_BUSNO_shift) |
                     (devfn << CYGARC_REG_PCI_CFG_ADDR_FUNC_shift) |
                     (offset & ~3));
    HAL_WRITE_UINT32(CYGARC_REG_PCI_CFG_CMD, CYGARC_REG_PCI_CFG_CMD_RCFG);
    _DELAY();
    HAL_READ_UINT32(CYGARC_REG_PCI_CFG_DATA, config_dword);

    return (cyg_uint8)((config_dword >> ((offset & 3) * 8)) & 0xff);
}

Example #5

File: suspend-stx7111.c Project: amalrajt/linux-sh4-2.6.23.17_stm23_A18B

IMMEDIATE_DEST(0x10000),
/* 3. Restore the previous clocks setting */
CLK_STORE(CKGA_OSC_DIV_CFG(4)),
DATA_LOAD(0x0),
CLK_STORE(CKGA_CLKOPSRC_SWITCH_CFG(0x0)),
DATA_LOAD(0x1),
CLK_STORE(CKGA_CLKOPSRC_SWITCH_CFG(0x1)),
DATA_LOAD(0x2),
CLK_STORE(CKGA_OSC_DIV_CFG(0x0)),
DATA_LOAD(0x3),
CLK_STORE(CKGA_OSC_DIV_CFG(5)),
DATA_LOAD(0x4),
CLK_STORE(CKGA_OSC_DIV_CFG(17)),

_DELAY(),
_DELAY(),
_DELAY(),
_END()
};

static unsigned long stx7111_wrt_table[16] __cacheline_aligned;

static int stx7111_suspend_prepare(suspend_state_t state)
{
#ifdef CONFIG_PM_DEBUG
	if (state == PM_SUSPEND_STANDBY) {
		stx7111_wrt_table[0] = /* swith config */
		   ioread32(CLOCKGENA_BASE_ADDR + CKGA_CLKOPSRC_SWITCH_CFG(0));
		stx7111_wrt_table[1] = /* clk_STNoc_ic */
		    ioread32(CLOCKGENA_BASE_ADDR + CKGA_OSC_DIV_CFG(0));