//------------------------------------------------------------------------------
/// Selection of Master Clock.
/// \param clockSource Master Clock source.
/// \param mckr MCKR configuration instance.
///
/// \note
/// The PMC_MCKR register must not be programmed in a single write
/// operation (see. Product Data Sheet).
//------------------------------------------------------------------------------
void PMC_SetMckSelection(unsigned int clockSource, mckrConfiguration *mckr)
{
switch ( clockSource )
{
case AT91C_PMC_CSS_SLOW_CLK :
PMC_SwitchMck2SlowClock();
_PMC_SetMckPrescaler(mckr->prescaler);
break;
case AT91C_PMC_CSS_MAIN_CLK :
_PMC_SwitchMck2MainClock();
_PMC_SetMckPrescaler(mckr->prescaler);
break;
#if defined ( AT91C_PMC_CSS_PLLA_CLK)
case AT91C_PMC_CSS_PLLA_CLK :
_PMC_SetMckPrescaler(mckr->prescaler);
_PMC_SwitchMck2PllaClock(mckr);
break ;
#endif
#if defined ( AT91C_PMC_CSS_PLL_CLK)
case AT91C_PMC_CSS_PLL_CLK :
_PMC_SetMckPrescaler(mckr->prescaler);
_PMC_SwitchMck2PllaClock(mckr);
break ;
#endif
}
}
/**
* \brief Configure PLL as clock input for MCK.
*
* \param mul PLL multiplier factor (not shifted, don't minus 1).
* \param div PLL divider factor (not shifted).
* \param prescaler Master Clock prescaler (shifted as in register).
*/
extern void PMC_ConfigureMckWithPll(uint32_t mul, uint32_t div, uint32_t prescaler)
{
/* First, select Main OSC as input clock for MCK */
_PMC_SwitchMck2MainClock();
/* Then, Set PLL clock */
PMC_SetPllClock(mul, div);
/* Wait until the master clock is established for the case we already turn on the PLL */
while( !(PMC->PMC_SR & PMC_SR_MCKRDY) );
/* Finally, select Pll as input clock for MCK */
PMC_SetMckSelection(PMC_MCKR_CSS_PLL_CLK, prescaler);
}
/**
* \brief Selection of Master Clock.
*
* \param clockSource Master Clock source.
* \param prescaler Master Clock prescaler.
*
* \note
* The PMC_MCKR register must not be programmed in a single write
* operation (see. Product Data Sheet).
*/
void PMC_SetMckSelection(uint32_t clockSource, uint32_t prescaler)
{
switch ( clockSource ) {
case PMC_MCKR_CSS_SLOW_CLK :
_PMC_SwitchMck2SlowClock();
_PMC_SetMckPrescaler(prescaler);
break;
case PMC_MCKR_CSS_MAIN_CLK :
_PMC_SwitchMck2MainClock();
_PMC_SetMckPrescaler(prescaler);
break;
case PMC_MCKR_CSS_PLLA_CLK :
_PMC_SetMckPrescaler(prescaler);
_PMC_SwitchMck2PllaClock();
break ;
}
}
/**
* \brief Disable all clocks.
*/
extern void PMC_DisableAllClocks(void)
{
uint32_t read_reg;
PMC->PMC_SCDR = PMC_SCDR_PCK0 | PMC_SCDR_PCK1 | PMC_SCDR_PCK2; /* disable PCK */
_PMC_SwitchMck2MainClock();
PMC->CKGR_PLLR = PMC->CKGR_PLLR & ~CKGR_PLLR_MUL_Msk; /* disable PLL A */
_PMC_SwitchMck2SlowClock();
read_reg = PMC->CKGR_MOR;
read_reg = (read_reg & ~CKGR_MOR_MOSCRCEN) | CKGR_MOR_KEY(0x37u); /* disable RC OSC */
PMC->CKGR_MOR = read_reg;
PMC_DisableAllPeripherals(); /* disable all peripheral clocks */
}
/**
* \brief Disable all clocks.
*/
void PMC_DisableAllClocks(void)
{
uint32_t read_reg;
PMC->PMC_SCDR = PMC_SCDR_PCK0 | PMC_SCDR_PCK1 | PMC_SCDR_PCK2 | PMC_SCDR_PCK3 |
PMC_SCDR_PCK4 | PMC_SCDR_PCK5 | PMC_SCDR_PCK6; /* disable PCK */
_PMC_SwitchMck2MainClock();
PMC->CKGR_PLLAR = PMC->CKGR_PLLAR & ~CKGR_PLLAR_MULA_Msk; /* disable PLL A */
_PMC_SwitchMck2SlowClock();
read_reg = PMC->CKGR_MOR;
read_reg = (read_reg & ~CKGR_MOR_MOSCRCEN) | CKGR_MOR_KEY_PASSWD;
/* disable RC OSC */
PMC->CKGR_MOR = read_reg;
PMC_DisableAllPeripherals(); /* disable all peripheral clocks */
}
