/** * @brief DeInitializes the FSMC_NAND device * @param Device Pointer to NAND device instance * @param Bank NAND bank number * @retval HAL status */ HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank) { /* Disable the NAND Bank */ __FSMC_NAND_DISABLE(Device, Bank); /* De-initialize the NAND Bank */ if(Bank == FSMC_NAND_BANK2) { /* Set the FSMC_NAND_BANK2 registers to their reset values */ Device->PCR2 = 0x00000018U; Device->SR2 = 0x00000040U; Device->PMEM2 = 0xFCFCFCFCU; Device->PATT2 = 0xFCFCFCFCU; } /* FSMC_Bank3_NAND */ else { /* Set the FSMC_NAND_BANK3 registers to their reset values */ Device->PCR3 = 0x00000018U; Device->SR3 = 0x00000040U; Device->PMEM3 = 0xFCFCFCFCU; Device->PATT3 = 0xFCFCFCFCU; } return HAL_OK; }
/** * @brief DeInitializes the FSMC_NAND device * @param Device: Pointer to NAND device instance * @param Bank: NAND bank number * @retval HAL status */ HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank) { /* Check the parameters */ assert_param(IS_FSMC_NAND_DEVICE(Device)); assert_param(IS_FSMC_NAND_BANK(Bank)); /* Disable the NAND Bank */ __FSMC_NAND_DISABLE(Device, Bank); /* De-initialize the NAND Bank */ if(Bank == FSMC_NAND_BANK2) { /* Set the FSMC_NAND_BANK2 registers to their reset values */ WRITE_REG(Device->PCR2, 0x00000018); WRITE_REG(Device->SR2, 0x00000040); WRITE_REG(Device->PMEM2, 0xFCFCFCFC); WRITE_REG(Device->PATT2, 0xFCFCFCFC); } /* FSMC_Bank3_NAND */ else { /* Set the FSMC_NAND_BANK3 registers to their reset values */ WRITE_REG(Device->PCR3, 0x00000018); WRITE_REG(Device->SR3, 0x00000040); WRITE_REG(Device->PMEM3, 0xFCFCFCFC); WRITE_REG(Device->PATT3, 0xFCFCFCFC); } return HAL_OK; }