/** * @brief Suspend callback. * @param hpcd: PCD handle * @retval None */ void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd) { if(hpcd->Instance == USB_OTG_HS) { #ifdef USE_USB_HS_IN_FS __HAL_PCD_GATE_PHYCLOCK(hpcd); USBD_LL_Suspend(hpcd->pData); /*Enter in STOP mode */ if (hpcd->Init.low_power_enable) { /* Set SLEEPDEEP bit and SleepOnExit of Cortex System Control Register */ SCB->SCR |= (uint32_t)((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk)); } #endif } else { __HAL_PCD_GATE_PHYCLOCK(hpcd); USBD_LL_Suspend(hpcd->pData); /*Enter in STOP mode */ if (hpcd->Init.low_power_enable) { /* Set SLEEPDEEP bit and SleepOnExit of Cortex System Control Register */ SCB->SCR |= (uint32_t)((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk)); } } }
/** * @brief HAL_PCDEx_LPM_Callback : Send LPM message to user layer * @param hpcd: PCD handle * @param msg: LPM message * @retval HAL status */ void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg) { switch ( msg) { case PCD_LPM_L0_ACTIVE: if (hpcd->Init.low_power_enable) { SystemClock_Config(); /* Reset SLEEPDEEP bit of Cortex System Control Register */ SCB->SCR &= (uint32_t)~((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk)); } __HAL_PCD_UNGATE_PHYCLOCK(hpcd); USBD_LL_Resume(hpcd->pData); break; case PCD_LPM_L1_ACTIVE: __HAL_PCD_GATE_PHYCLOCK(hpcd); USBD_LL_Suspend(hpcd->pData); /*Enter in STOP mode */ if (hpcd->Init.low_power_enable) { /* Set SLEEPDEEP bit and SleepOnExit of Cortex System Control Register */ SCB->SCR |= (uint32_t)((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk)); } break; } }
/** * @brief Suspend callback. * @param hpcd: PCD handle * @retval None */ void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd) { __IO uint32_t i=0; if(hpcd->Instance == USB_OTG_HS) { __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT(); __HAL_PCD_GATE_PHYCLOCK(hpcd); /* Wait timeout of 6 ULPI PHY clock ~= 18 cpu clocks */ for (i=0; i<18; i++) { __NOP(); } if (__HAL_PCD_IS_PHY_SUSPENDED(hpcd)) /* when set then false resume condition*/ { __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG(); __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT(); USBD_LL_Suspend(hpcd->pData); /*Enter in STOP mode */ if (hpcd->Init.low_power_enable) { /* Set SLEEPDEEP bit and SleepOnExit of Cortex System Control Register */ SCB->SCR |= (uint32_t)((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk)); } } } else { __HAL_PCD_GATE_PHYCLOCK(hpcd); USBD_LL_Suspend(hpcd->pData); /*Enter in STOP mode */ if (hpcd->Init.low_power_enable) { /* Set SLEEPDEEP bit and SleepOnExit of Cortex System Control Register */ SCB->SCR |= (uint32_t)((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk)); } } }
/** * @brief Suspend callback. * @param hpcd: PCD handle * @retval None */ void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd) { USBD_LL_Suspend(hpcd->pData); __HAL_PCD_GATE_PHYCLOCK(hpcd); /*Enter in STOP mode */ if (hpcd->Init.low_power_enable) { /* Set SLEEPDEEP bit and SleepOnExit of Cortex System Control Register */ SCB->SCR |= (uint32_t)((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk)); } }
/** * @brief Suspend callback. * When Low power mode is enabled the debug cannot be used (IAR, Keil doesn't support it) * @param hpcd: PCD handle * @retval None */ void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd) { /* Inform USB library that core enters in suspend Mode */ USBD_LL_Suspend(hpcd->pData); __HAL_PCD_GATE_PHYCLOCK(hpcd); /*Enter in STOP mode */ /* USER CODE BEGIN 2 */ if (hpcd->Init.low_power_enable) { /* Set SLEEPDEEP bit and SleepOnExit of Cortex System Control Register */ SCB->SCR |= (uint32_t)((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk)); } /* USER CODE END 2 */ }