void eventTickStart(void)
{
//*TDATA0 = countdown; /* load Counter Timer ... */
//*TMOD |= 0x1; /* enable interval interrupt ... */
__REG32(TIMER_BASE + OSCR) = 0x00000000; // Count Clear
__REG32(TIMER_BASE + OIER) |= 0x00000001; // TIMER 0 : set bit 0 -> 1
__REG32(TIMER_BASE + OSSR) = 0x00000001; // Timer Status Clear
/* -- unmask the interrupt source.. */
//*(volatile unsigned int*)INTMSK &= ~((1 << INT_GLOBAL) | (1<<10) | (1<<0));
}
void eventTickService(void)
{
/* -- reset timer interrupt... */
disable_irq(); // Disable IRQ
if((__REG32(INTERRUPT_CONTROL_BASE + ICIP) & 0x04000000) != 0x00000000){ // pin 26 : OS Timer 0 // if IRQ set, bit 26 set 1. So if it's value same with 0x00000000, not set IRQ
__REG32(TIMER_BASE + OSCR) = 0x00000000; // OSCR = 0
__REG32(TIMER_BASE + OSSR) &= 0x00000000; // OSSR : 0 -> 1
__REG32(TIMER_BASE + OSSR) |= 0x00000001; // if OSMR and OSCR have same value, OSSR set bit 0 : 1
}
/* -- unmask the interrupt source.... */
enable_irq(); // IRQ Enable
//*(volatile unsigned int*)INTMSK &= ~((1<<INT_GLOBAL)|(1<<10)|(1<<0));
}
void eventTickInit (UINT msec)
{
/* ----------------------------------------------------------------------
*
* Initalize the Tick hardware on the Samsung part.
*
* ----------------------------------------------------------------------
*/
__REG32(INTERRUPT_CONTROL_BASE + ICCR) = 0x00000001; // Disable Idle Mask = DIM = idel mode on : bit 0 -> 1
__REG32(INTERRUPT_CONTROL_BASE + ICMR) |= 0x04000000; // TIMTER 0 MASK : bit 26 -> 1
__REG32(INTERRUPT_CONTROL_BASE + ICLR) &= 0x00000000; // IRQ mode : IL26 = 0
__REG32(TIMER_BASE + OSCR) = 0x00000000; // Count Clear
__REG32(TIMER_BASE + OSSR) = 0x00000001; // Timer Status Clear
/* ----------------------------------------------------------------------
*
* Set the countdown value depending on msec.
*
* ----------------------------------------------------------------------
*/
switch (msec)
{
case 2: /* fast ... */
__REG32(TIMER_BASE + OSMR0) = 368640; // 0.1sec -> 368640
break;
default: /* slow ... */
__REG32(TIMER_BASE + OSMR0) = 3686400; // 1sec -> 3686400
break;
}
}
/*TODO Have separte definitions in i2c-bcm1161.h
* Clock enabling has to be done in clk manager
*/
void setrate(void *base, struct bcm1161_i2c *i2c, unsigned short spd)
{
unsigned char I2C_M = 1, I2C_N = 1;
unsigned char DIV = I2CTIM_DIV_1625000HZ, I2C_P = 2;
int temp = 0;
#ifdef CONFIG_ARCH_BCM215XX
unsigned char NO_DIV = 0, PRESCALE = I2C_MM_HS_TIM_PRESCALE_CMD_NODIV;
__REG32(CLK_HSBSC_ENABLE) = 1;
__REG32(CLK_HSBSC2_ENABLE) = 1;
#endif
if (i2c->cur_spd != spd) {
switch (spd) {
case I2C_SPD_32K:
I2C_M = 0x01;
I2C_N = 0x01;
DIV = I2CTIM_DIV_812500HZ;
I2C_P = 0x04;
break;
case I2C_SPD_50K:
I2C_M = 0x01;
I2C_N = 0x01;
DIV = I2CTIM_DIV_812500HZ;
I2C_P = 0x02;
break;
case I2C_SPD_220K:
I2C_M = 0x07;
I2C_N = 0x00;
DIV = I2CTIM_DIV_3250000HZ;
I2C_P = 0x00;
break;
case I2C_SPD_360K:
I2C_M = 0x02;
I2C_N = 0x04;
DIV = I2CTIM_DIV_6500000HZ;
I2C_P = 0x01;
break;
case I2C_SPD_400K:
case I2C_SPD_MAXIMUM:
I2C_M = 0x02;
I2C_N = 0x02;
DIV = I2CTIM_DIV_6500000HZ;
I2C_P = 0x01;
break;
case I2C_SPD_100K:
default:
I2C_M = 0x01;
I2C_N = 0x01;
DIV = I2CTIM_DIV_3250000HZ;
I2C_P = 0x06;
break;
}
i2c->cur_spd = spd;
temp = (I2C_P << 3) | DIV;
#ifdef CONFIG_ARCH_BCM215XX
temp |= (NO_DIV << 2) | (PRESCALE << 6);
#endif
REG_I2C_TIM(base) = temp;
REG_I2C_CLKEN(base) = (REG_I2C_CLKEN(base) &
REG_I2C_CLKEN_AUTOSENSE_EN) |
(I2C_M << 4) | (I2C_N << 1) | REG_I2C_CLKEN_CLKEN;
}
return 0;
/* pr_info("setrate rate=%d, m=%d, n=%d, p=%d, div=%d, tim=0x%X,
clk_en=0x%X\n", spd, I2C_M, I2C_N, I2C_P, DIV,
REG_I2C_TIM(base), REG_I2C_CLKEN(base)); */
}
