static int cgm_read_proc (char *page, char **start, off_t off, int count, int *eof, void *data) { int len = 0; unsigned int cppcr = REG_CPM_CPPCR; /* PLL Control Register */ unsigned int cpccr = REG_CPM_CPCCR; /* Clock Control Register */ unsigned int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32}; unsigned int od[4] = {1, 2, 2, 4}; len += sprintf (page+len, "CPPCR : 0x%08x\n", cppcr); len += sprintf (page+len, "CPCCR : 0x%08x\n", cpccr); len += sprintf (page+len, "PLL : %s\n", (cppcr & CPM_CPPCR_PLLEN) ? "ON" : "OFF"); len += sprintf (page+len, "m:n:o : %d:%d:%d\n", __cpm_get_pllm() + 2, __cpm_get_plln() + 2, od[__cpm_get_pllod()] ); len += sprintf (page+len, "C:H:M:P : %d:%d:%d:%d\n", div[__cpm_get_cdiv()], div[__cpm_get_hdiv()], div[__cpm_get_mdiv()], div[__cpm_get_pdiv()] ); len += sprintf (page+len, "PLL Freq : %3d.%02d MHz\n", TO_MHZ(__cpm_get_pllout())); len += sprintf (page+len, "CCLK : %3d.%02d MHz\n", TO_MHZ(__cpm_get_cclk())); len += sprintf (page+len, "HCLK : %3d.%02d MHz\n", TO_MHZ(__cpm_get_hclk())); len += sprintf (page+len, "MCLK : %3d.%02d MHz\n", TO_MHZ(__cpm_get_mclk())); len += sprintf (page+len, "PCLK : %3d.%02d MHz\n", TO_MHZ(__cpm_get_pclk())); len += sprintf (page+len, "LCDCLK : %3d.%02d MHz\n", TO_MHZ(__cpm_get_lcdclk())); len += sprintf (page+len, "PIXCLK : %3d.%02d KHz\n", TO_KHZ(__cpm_get_pixclk())); len += sprintf (page+len, "I2SCLK : %3d.%02d MHz\n", TO_MHZ(__cpm_get_i2sclk())); len += sprintf (page+len, "USBCLK : %3d.%02d MHz\n", TO_MHZ(__cpm_get_usbclk())); len += sprintf (page+len, "MSC0CLK : %3d.%02d MHz\n", TO_MHZ(__cpm_get_mscclk(0))); len += sprintf (page+len, "MSC1CLK : %3d.%02d MHz\n", TO_MHZ(__cpm_get_mscclk(1))); len += sprintf (page+len, "EXTALCLK0 : %3d.%02d MHz\n", TO_MHZ(__cpm_get_extalclk0())); len += sprintf (page+len, "EXTALCLK(by CPM): %3d.%02d MHz\n", TO_MHZ(__cpm_get_extalclk())); len += sprintf (page+len, "RTCCLK : %3d.%02d MHz\n", TO_MHZ(__cpm_get_rtcclk())); return len; }
static void __init sysclocks_setup(void) { #ifndef CONFIG_MIPS_JZ_EMURUS /* FPGA */ jz_clocks.cclk = __cpm_get_cclk(); jz_clocks.hclk = __cpm_get_hclk(); jz_clocks.pclk = __cpm_get_pclk(); jz_clocks.mclk = __cpm_get_mclk(); jz_clocks.h1clk = __cpm_get_h1clk(); jz_clocks.pixclk = __cpm_get_pixclk(); jz_clocks.i2sclk = __cpm_get_i2sclk(); jz_clocks.usbclk = __cpm_get_usbclk(); jz_clocks.mscclk = __cpm_get_mscclk(0); jz_clocks.extalclk = __cpm_get_extalclk(); jz_clocks.rtcclk = __cpm_get_rtcclk(); #else #define FPGACLK 8000000 jz_clocks.cclk = FPGACLK; jz_clocks.hclk = FPGACLK; jz_clocks.pclk = FPGACLK; jz_clocks.mclk = FPGACLK; jz_clocks.h1clk = FPGACLK; jz_clocks.pixclk = FPGACLK; jz_clocks.i2sclk = FPGACLK; jz_clocks.usbclk = FPGACLK; jz_clocks.mscclk = FPGACLK; jz_clocks.extalclk = FPGACLK; jz_clocks.rtcclk = FPGACLK; #endif printk("CPU clock: %dMHz, System clock: %dMHz, Peripheral clock: %dMHz, Memory clock: %dMHz\n", (jz_clocks.cclk + 500000) / 1000000, (jz_clocks.hclk + 500000) / 1000000, (jz_clocks.pclk + 500000) / 1000000, (jz_clocks.mclk + 500000) / 1000000); }