void arch_vcpu_regs_dump(struct vmm_chardev *cdev, struct vmm_vcpu *vcpu) { struct arm_priv *p; /* For both Normal & Orphan VCPUs */ __cpu_vcpu_dump_user_reg(cdev, arm_regs(vcpu)); /* For only Normal VCPUs */ if (!vcpu->is_normal) { return; } /* Get private context */ p = arm_priv(vcpu); /* Hypervisor context */ vmm_cprintf(cdev, "Hypervisor EL2 Registers\n"); vmm_cprintf(cdev, " %11s=0x%016lx %11s=0x%016lx\n", "HCR_EL2", p->hcr, "CPTR_EL2", p->cptr); vmm_cprintf(cdev, " %11s=0x%016lx %11s=0x%016lx\n", "HSTR_EL2", p->hstr, "TTBR_EL2", arm_guest_priv(vcpu->guest)->ttbl->tbl_pa); /* Print VFP context */ cpu_vcpu_vfp_dump(cdev, vcpu); /* Print sysregs context */ cpu_vcpu_sysregs_dump(cdev, vcpu); }
void arch_vcpu_regs_dump(struct vmm_chardev *cdev, struct vmm_vcpu *vcpu) { u32 ite; /* For both Normal & Orphan VCPUs */ __cpu_vcpu_dump_user_reg(cdev, vcpu, arm_regs(vcpu)); /* For only Normal VCPUs */ if (!vcpu->is_normal) { return; } vmm_cprintf(cdev, " User Mode Registers (Banked)\n"); vmm_cprintf(cdev, " SP=0x%08x LR=0x%08x\n", arm_priv(vcpu)->sp_usr, arm_priv(vcpu)->lr_usr); vmm_cprintf(cdev, " Supervisor Mode Registers (Banked)\n"); vmm_cprintf(cdev, " SP=0x%08x LR=0x%08x SPSR=0x%08x\n", arm_priv(vcpu)->sp_svc, arm_priv(vcpu)->lr_svc, arm_priv(vcpu)->spsr_svc); vmm_cprintf(cdev, " Monitor Mode Registers (Banked)\n"); vmm_cprintf(cdev, " SP=0x%08x LR=0x%08x SPSR=0x%08x\n", arm_priv(vcpu)->sp_mon, arm_priv(vcpu)->lr_mon, arm_priv(vcpu)->spsr_mon); vmm_cprintf(cdev, " Abort Mode Registers (Banked)\n"); vmm_cprintf(cdev, " SP=0x%08x LR=0x%08x SPSR=0x%08x\n", arm_priv(vcpu)->sp_abt, arm_priv(vcpu)->lr_abt, arm_priv(vcpu)->spsr_abt); vmm_cprintf(cdev, " Undefined Mode Registers (Banked)\n"); vmm_cprintf(cdev, " SP=0x%08x LR=0x%08x SPSR=0x%08x\n", arm_priv(vcpu)->sp_und, arm_priv(vcpu)->lr_und, arm_priv(vcpu)->spsr_und); vmm_cprintf(cdev, " IRQ Mode Registers (Banked)\n"); vmm_cprintf(cdev, " SP=0x%08x LR=0x%08x SPSR=0x%08x\n", arm_priv(vcpu)->sp_irq, arm_priv(vcpu)->lr_irq, arm_priv(vcpu)->spsr_irq); vmm_cprintf(cdev, " FIQ Mode Registers (Banked)\n"); vmm_cprintf(cdev, " SP=0x%08x LR=0x%08x SPSR=0x%08x", arm_priv(vcpu)->sp_fiq, arm_priv(vcpu)->lr_fiq, arm_priv(vcpu)->spsr_fiq); for (ite = 0; ite < 5; ite++) { if (ite % 3 == 0) vmm_cprintf(cdev, "\n"); vmm_cprintf(cdev, " R%02d=0x%08x ", (ite + 8), arm_priv(vcpu)->gpr_fiq[ite]); } vmm_cprintf(cdev, "\n"); }
void cpu_vcpu_dump_user_reg(arch_regs_t *regs) { __cpu_vcpu_dump_user_reg(NULL, regs); }
void cpu_vcpu_dump_user_reg(struct vmm_vcpu *vcpu, arch_regs_t *regs) { __cpu_vcpu_dump_user_reg(NULL, vcpu, regs); }