int DST_InitDecoder(ebunch * D, int NrOfChannels, int SampleRate)
{
int retval = 0;
memset(D, 0, sizeof(ebunch));
D->FrameHdr.NrOfChannels = NrOfChannels;
/* 64FS => 4704 */
/* 128FS => 9408 */
/* 256FS => 18816 */
D->FrameHdr.MaxFrameLen = (588 * SampleRate / 8);
D->FrameHdr.ByteStreamLen = D->FrameHdr.MaxFrameLen * D->FrameHdr.NrOfChannels;
D->FrameHdr.BitStreamLen = D->FrameHdr.ByteStreamLen * RESOL;
D->FrameHdr.NrOfBitsPerCh = D->FrameHdr.MaxFrameLen * RESOL;
D->FrameHdr.MaxNrOfFilters = 2 * D->FrameHdr.NrOfChannels;
D->FrameHdr.MaxNrOfPtables = 2 * D->FrameHdr.NrOfChannels;
D->FrameHdr.FrameNr = 0;
D->StrFilter.TableType = FILTER;
D->StrPtable.TableType = PTABLE;
if (retval==0)
{
AllocateDecMemory(D);
}
if (retval==0)
{
retval = CCP_CalcInit(&D->StrFilter);
}
if (retval==0)
{
retval = CCP_CalcInit(&D->StrPtable);
}
D->SSE2 = 0;
#if !defined(NO_SSE2) && (defined(_M_IX86) || defined(_M_X64) || defined(__i386__) || defined(__x86_64__))
{
int CPUInfo[4];
#if defined(__i386__) || defined(__x86_64__)
#define cpuid(type, a, b, c, d) \
__asm__ ("cpuid":\
"=a" (a), "=b" (b), "=c" (c), "=d" (d) : "a" (type));
cpuid(1, CPUInfo[0], CPUInfo[1], CPUInfo[2], CPUInfo[3]);
#else
__cpuid(CPUInfo, 1);
#endif
D->SSE2 = (CPUInfo[3] & (1L << 26)) ? 1 : 0;
}
#endif
return(retval);
}
void GetCPUId(DWORD type, DWORD* EAX, DWORD* EBX, DWORD* ECX, DWORD* EDX)
{
int CPUInfo[4];
__cpuid(CPUInfo, type);
*EAX = CPUInfo[0];
*EBX = CPUInfo[1];
*ECX = CPUInfo[2];
*EDX = CPUInfo[3];
}
bool F2M_HardwareSupportsSIMD()
{
unsigned int CPUInfo[4];
#ifdef WIN32
__cpuid((int*)CPUInfo, 1);
#else
__get_cpuid(1, &CPUInfo[0], &CPUInfo[1], &CPUInfo[2], &CPUInfo[3]);
#endif
bool sse = ((CPUInfo[3] & (1 << 26)) != 0);
return sse;
}
int KSC_GetSIMDWidth()
{
int CPUInfo[4];
__cpuid(CPUInfo, 1);
bool hasSSE = (CPUInfo[3] & (1 << 25));
const unsigned AVXBits = (1 << 27) | (1 << 28);
bool HasAVX = ((CPUInfo[2] & AVXBits) == AVXBits);
return HasAVX ? 8 : (hasSSE ? 4 : 1);
}
void cpuID(unsigned i, int regs[4]) {
#ifdef _WIN32
__cpuid((int *)regs, (int)i);
#else
asm volatile
("cpuid" : "=a" (regs[0]), "=b" (regs[1]), "=c" (regs[2]), "=d" (regs[3])
: "a" (i), "c" (0));
// ECX is set to zero for CPUID function 4
#endif
}
DeviceInfo::DeviceInfo()
{
#if ALICE_SUPPORT_SSE
int data[4] = { 0 };
// Add more code here to extract vendor string or what ever is needed
__cpuid(data, 0);
if (data[0] >= 1) {
__cpuid(data, 1);
m_CPUIDFeatures = data[3];
}
m_IsSSESupported = (m_CPUIDFeatures & CPUID_FEATURES_SSE) != 0;
m_IsSSE2Supported = (m_CPUIDFeatures & CPUID_FEATURES_SSE2) != 0;
#elif ALICE_ANDROID && ALICE_SUPPORTS_NEON
m_CPUIDFeatures = android_getCpuFeatures();
m_IsNEONSupported = (m_CPUIDFeatures & ANDROID_CPU_ARM_FEATURE_NEON) != 0;
#endif
m_Initialized = true;
}
// HelpIsROCefAvailable
bool HelpIsROCefAvailable()
{
bool result = false;
int aCPUInfo[NUM_CPUID_OFFSETS] = { -1 };
__cpuid(aCPUInfo, CPUID_FnAdvancePowerManagementInformation);
// Effective Frequency is supported
result = (aCPUInfo[EDX_OFFSET] & CPUID_FnAdvancePowerManagementInformation_EDX_EffFreqRO) != 0;
return result;
}
extern void pt_cpuid(uint32_t leaf, uint32_t *eax, uint32_t *ebx,
uint32_t *ecx, uint32_t *edx)
{
int cpu_info[4];
__cpuid(cpu_info, leaf);
*eax = cpu_info[0];
*ebx = cpu_info[1];
*ecx = cpu_info[2];
*edx = cpu_info[3];
}
// HelpIsCefSupported: Check if core effective frequency feature is available
bool HelpIsCefSupported()
{
bool result = false;
int aCPUInfo[NUM_CPUID_OFFSETS] = { -1 };
__cpuid(aCPUInfo, CPUID_FnThermalAndPowerManagement);
// Effective Frequency is supported
result = (aCPUInfo[ECX_OFFSET] & CPUID_FnThermalAndPowerManagement_ECX_EffFreq) != 0;
return result;
}
static void getSSELevelSupport(int* hasSSE2_out, int* hasSSE3_out)
{
int nIds = 0;
int cpuInfo[4] = { 0, 0, 0, 0 };
int hasSSE2 = FALSE;
int hasSSE3 = FALSE;
__cpuid(cpuInfo, 0);
nIds = cpuInfo[0];
if (nIds >= 1)
{
__cpuid(cpuInfo, 1);
hasSSE2 = !!(cpuInfo[3] & bit_SSE2);
hasSSE3 = !!(cpuInfo[2] & bit_SSE3);
}
*hasSSE2_out = hasSSE2;
*hasSSE3_out = hasSSE3;
}
void cpuid(int level, unsigned int* a, unsigned int* b,
unsigned int* c, unsigned int* d)
{
unsigned int eax, ebx, ecx, edx;
__cpuid(level, eax, ebx, ecx, edx);
*a = eax;
*b = ebx;
*c = ecx;
*d = edx;
}
/*Chech&set the instruction set of CPU*/
void set_CPU_instruction()
{
unsigned int cpuid_results[4];
__cpuid(cpuid_results,7);
if(cpuid_results[1] &(1 << 16))
{
#define RTE_MACHINE_CPUFLAG_AVX512F //comes from DPDK ^^
log_info("CPU Instruction set:AVX512F");
return;
}
if(cpuid_results[1] & (1 << 5))
{
#define RTE_MACHINE_CPUFLAG_AVX2
log_info("CPU Instruction set:AVX2");
return;
}
__cpuid(cpuid_results,1);
if(cpuid_results[3] & (1 << 25))
log_info("CPU Instruction set:SSE");
}
void
ethr_x86_cpuid__(int *eax, int *ebx, int *ecx, int *edx)
{
int CPUInfo[4];
__cpuid(CPUInfo, *eax);
*eax = CPUInfo[0];
*ebx = CPUInfo[1];
*ecx = CPUInfo[2];
*edx = CPUInfo[3];
}
unsigned short getCpuHash()
{
int cpuinfo[4] = { 0, 0, 0, 0 };
unsigned short hash = 0;
__cpuid(cpuinfo, 0);
unsigned short* ptr = (unsigned short*)(&cpuinfo[0]);
for (unsigned int i = 0; i < 8; i++ )
hash += ptr[i];
return hash;
}
// HelpIsPMCCounterAvailable
bool HelpIsPMCCounterAvailable()
{
bool result = false;
int aCPUInfo[NUM_CPUID_OFFSETS] = { -1 };
__cpuid(aCPUInfo, CPUID_FnAmdExtendedFeatures);
// Effective Frequency is supported
result = (aCPUInfo[EDX_OFFSET] & CPUID_FnAmdExtendedFeatures_ECX_PerfCtrExtCore) != 0;
return result;
}
static int IsMMX( void )
{
unsigned regs[4];
// get CPU feature bits
__cpuid( regs, 1 );
// bit 23 of EDX denotes MMX existence
if ( regs[3] & ( 1 << 23 ) )
return qtrue;
return qfalse;
}
// getCpuid: Rea CPU instruction id
static AMDTResult getCpuid(AMDTUInt32 fn, AMDTInt32 cpuInfo[4])
{
#if ( defined (_WIN32) || defined (_WIN64) )
__cpuid(cpuInfo, fn);
#else
// Linux
#if defined(__i386__) && defined(__PIC__)
/* %ebx may be the PIC register. */
#define __cpuid(level, a, b, c, d) \
__asm__("xchgl\t%%ebx, %1\n\t" \
"cpuid\n\t" \
"xchgl\t%%ebx, %1\n\t" \
: "=a" (a), "=r" (b), "=c" (c), "=d" (d) \
: "0" (level))
#else
#define __cpuid(level, a, b, c, d) \
__asm__("cpuid\n\t" \
: "=a" (a), "=b" (b), "=c" (c), "=d" (d) \
: "0" (level))
#endif
AMDTUInt32 eax;
AMDTUInt32 ebx;
AMDTUInt32 ecx;
AMDTUInt32 edx;
/* CPUID Fn0000_0001_EAX Family, Model, Stepping */
__cpuid(fn, eax, ebx, ecx, edx);
cpuInfo[0] = eax;
cpuInfo[1] = ebx;
cpuInfo[2] = ecx;
cpuInfo[3] = edx;
#endif
return AMDT_STATUS_OK;
}
void init_functions ()
{
int out [4];
__cpuid (out, 1);
BOOL sse42 = (out [2] & (1 << 20)) != 0;
BOOL sse41 = (out [2] & (1 << 19)) != 0;
BOOL fma = (out [2] & (1 << 12)) != 0;
BOOL avx = (out [2] & (1 << 28)) != 0;
BOOL osxsave = (out [2] & (1 << 29)) != 0;
__cpuidex (out, 7, 0);
BOOL avx2 = (out [1] & 0x20) != 0;
int i = 0;
funcs [i] = calculate_float; method_names [i] = "float"; if (full_mode) i++;
if (sse42) {
funcs [i] = calculate_sse_float; method_names [i] = "float SSE"; if (full_mode) i++;
}
if (osxsave && avx) {
funcs [i] = calculate_avx_float; method_names [i] = "float AVX"; if (full_mode) i++;
}
if (osxsave && avx && avx2) {
funcs [i] = calculate_avx2_float; method_names [i] = "float AVX2"; if (full_mode) i++;
}
if (osxsave && avx && avx2 && fma) {
funcs [i] = calculate_fma_float; method_names [i] = "float FMA"; if (full_mode) i++;
}
if (!full_mode) i++;
funcs [i] = calculate_double; method_names [i] = "double"; if (full_mode) i++;
if (sse42) {
funcs [i] = calculate_sse_double; method_names [i] = "double SSE"; if (full_mode) i++;
}
if (osxsave && avx) {
funcs [i] = calculate_avx_double; method_names [i] = "double AVX"; if (full_mode) i++;
}
if (osxsave && avx && avx2) {
funcs [i] = calculate_avx2_double; method_names [i] = "double AVX2"; if (full_mode) i++;
}
if (osxsave && avx && avx2 && fma) {
funcs [i] = calculate_fma_double; method_names [i] = "double FMA"; if (full_mode) i++;
}
if (!full_mode) i++;
func_count = i;
func_index = 0;
calculate_func = funcs [func_index];
}
bool
AutoSystemInfo::CheckForAtom() const
{
int CPUInfo[4];
const int GENUINE_INTEL_0 = 0x756e6547,
GENUINE_INTEL_1 = 0x49656e69,
GENUINE_INTEL_2 = 0x6c65746e;
const int PLATFORM_MASK = 0x0fff3ff0;
const int ATOM_PLATFORM_A = 0x0106c0, /* bonnell - extended model 1c, type 0, family code 6 */
ATOM_PLATFORM_B = 0x020660, /* lincroft - extended model 26, type 0, family code 6 */
ATOM_PLATFORM_C = 0x020670, /* saltwell - extended model 27, type 0, family code 6 */
ATOM_PLATFORM_D = 0x030650, /* tbd - extended model 35, type 0, family code 6 */
ATOM_PLATFORM_E = 0x030660, /* tbd - extended model 36, type 0, family code 6 */
ATOM_PLATFORM_F = 0x030670; /* tbd - extended model 37, type 0, family code 6 */
int platformSignature;
__cpuid(CPUInfo, 0);
// See if CPU is ATOM HW. First check if CPU is genuine Intel.
if( CPUInfo[1]==GENUINE_INTEL_0 &&
CPUInfo[3]==GENUINE_INTEL_1 &&
CPUInfo[2]==GENUINE_INTEL_2)
{
__cpuid(CPUInfo, 1);
// get platform signature
platformSignature = CPUInfo[0];
if((( PLATFORM_MASK & platformSignature) == ATOM_PLATFORM_A) ||
((PLATFORM_MASK & platformSignature) == ATOM_PLATFORM_B) ||
((PLATFORM_MASK & platformSignature) == ATOM_PLATFORM_C) ||
((PLATFORM_MASK & platformSignature) == ATOM_PLATFORM_D) ||
((PLATFORM_MASK & platformSignature) == ATOM_PLATFORM_E) ||
((PLATFORM_MASK & platformSignature) == ATOM_PLATFORM_F))
{
return true;
}
}
return false;
}
// »°µ√CPU≥߅ã®Vendor£©
//
// result: ≥…π¶ ±∑µªÿ◊÷∑˚¥Æµƒ≥§∂»£®“ª∞„Œ™12£©°£ ß∞‹ ±∑µªÿ0°£
// pvendor: Ω” ’≥߅Ö≈œ¢µƒ◊÷∑˚¥Æª∫≥«¯°£÷¡…ŸŒ™13◊÷Ω⁄°£
int get_cpu_vendor(char* pvendor)
{
INT32 dwBuf[4];
if (NULL==pvendor) return 0;
// Function 0: Vendor-ID and Largest Standard Function
__cpuid(dwBuf, 0);
// save. ±£¥ÊµΩpvendor
*(INT32*)&pvendor[0] = dwBuf[1]; // ebx: «∞Àƒ∏ˆ◊÷∑�?
*(INT32*)&pvendor[4] = dwBuf[3]; // edx: ÷–º‰Àƒ∏ˆ◊÷∑�?
*(INT32*)&pvendor[8] = dwBuf[2]; // ecx: ◊Ó∫ÛÀƒ∏ˆ◊÷∑�?
pvendor[12] = '\0';
return 12;
}
CPUInfo __stdcall cpuid(int InfoType)
{
int results[4];
__cpuid(results, InfoType);
CPUInfo i;
i.Part1 = results[0];
i.Part2 = results[1];
i.Part3 = results[2];
i.Part4 = results[3];
return i;
}
/**
* Checks the SSE2 feature bit returned by the CPUID instruction
* @return Does the CPU support SSE2?
*/
bool Zoom::haveSSE2()
{
#ifdef __GNUC__
unsigned int CPUInfo[4] = {0, 0, 0, 0};
__get_cpuid(1, CPUInfo, CPUInfo+1, CPUInfo+2, CPUInfo+3);
#elif _WIN32
int CPUInfo[4];
__cpuid(CPUInfo, 1);
#else
unsigned int CPUInfo[4] = {0, 0, 0, 0};
#endif
return (CPUInfo[3] & 0x04000000) ? true : false;
}
static bool is_sse4_2_supported(void)
{
#if defined(__SSE42__) && (defined(__i386__) || defined(__x86_64__))
unsigned int eax, ebx, ecx, edx;
#ifdef __APPLE__
__get_cpuid(1, &eax, &ebx, &ecx, &edx);
#else
__cpuid(1, eax, ebx, ecx, edx);
#endif
return ecx & 0x00080000; // SSE4.2
#else
return false;
#endif
}
int check_for_aes_instructions()
{
unsigned int cpuid_results[4];
int yes=1, no=0;
// Removed checks for Intel CPU -HN
__cpuid(cpuid_results,1);
if (cpuid_results[2] & AES_INSTRCTIONS_CPUID_BIT)
return yes;
return no;
}
SSE_VERSION GetSSEVersion()
{
int CPUInfo[4];
__cpuid(CPUInfo, 1);
if ((CPUInfo[2] & 0x80000)!=0)
return SSE_SSE41;
if ((CPUInfo[2] & 0x200)!=0)
return SSE_SSSE3;
if ((CPUInfo[3] & 0x4000000)!=0)
return SSE_SSE2;
if ((CPUInfo[3] & 0x2000000)!=0)
return SSE_SSE;
return SSE_NONE;
}
QString PlatformInfoScriptingInterface::getCPUBrand() {
#ifdef Q_OS_WIN
int CPUInfo[4] = { -1 };
unsigned nExIds, i = 0;
char CPUBrandString[0x40];
// Get the information associated with each extended ID.
__cpuid(CPUInfo, 0x80000000);
nExIds = CPUInfo[0];
for (i = 0x80000000; i <= nExIds; ++i) {
__cpuid(CPUInfo, i);
// Interpret CPU brand string
if (i == 0x80000002) {
memcpy(CPUBrandString, CPUInfo, sizeof(CPUInfo));
} else if (i == 0x80000003) {
memcpy(CPUBrandString + 16, CPUInfo, sizeof(CPUInfo));
} else if (i == 0x80000004) {
memcpy(CPUBrandString + 32, CPUInfo, sizeof(CPUInfo));
}
}
return CPUBrandString;
#elif defined Q_OS_MAC
FILE* stream = popen("sysctl -n machdep.cpu.brand_string", "r");
std::ostringstream hostStream;
while (!feof(stream) && !ferror(stream)) {
char buf[128];
int bytesRead = fread(buf, 1, 128, stream);
hostStream.write(buf, bytesRead);
}
return QString::fromStdString(hostStream.str());
#else
return QString("NO IMPLEMENTED");
#endif
}
void
AutoSystemInfo::Initialize()
{
Assert(!initialized);
processHandle = GetCurrentProcess();
GetSystemInfo(this);
// Make the page size constant so calculation are faster.
Assert(this->dwPageSize == AutoSystemInfo::PageSize);
#if defined(_M_IX86) || defined(_M_X64)
__cpuid(CPUInfo, 1);
isAtom = CheckForAtom();
#endif
#if defined(_M_ARM32_OR_ARM64)
armDivAvailable = IsProcessorFeaturePresent(PF_ARM_DIVIDE_INSTRUCTION_AVAILABLE) ? true : false;
#endif
allocationGranularityPageCount = dwAllocationGranularity / dwPageSize;
isWindows8OrGreater = IsWindows8OrGreater();
binaryName[0] = _u('\0');
dllLoadAddress = (UINT_PTR)&__ImageBase;
dllHighAddress = (UINT_PTR)&__ImageBase +
((PIMAGE_NT_HEADERS)(((char *)&__ImageBase) + __ImageBase.e_lfanew))->OptionalHeader.SizeOfImage;
InitPhysicalProcessorCount();
#if DBG
initialized = true;
#endif
WCHAR DisableDebugScopeCaptureFlag[MAX_PATH];
if (::GetEnvironmentVariable(_u("JS_DEBUG_SCOPE"), DisableDebugScopeCaptureFlag, _countof(DisableDebugScopeCaptureFlag)) != 0)
{
disableDebugScopeCapture = true;
}
else
{
disableDebugScopeCapture = false;
}
this->shouldQCMoreFrequently = false;
this->supportsOnlyMultiThreadedCOM = false;
this->isLowMemoryDevice = false;
// 0 indicates we haven't retrieved the available commit. We get it lazily.
this->availableCommit = 0;
::ChakraBinaryAutoSystemInfoInit(this);
}
ULONG
NTAPI
KiGetCpuVendor(VOID)
{
PKPRCB Prcb = KeGetCurrentPrcb();
INT Vendor[5];
/* Get the Vendor ID and null-terminate it */
__cpuid(Vendor, 0);
/* Copy it to the PRCB and null-terminate it */
*(ULONG*)&Prcb->VendorString[0] = Vendor[1]; // ebx
*(ULONG*)&Prcb->VendorString[4] = Vendor[3]; // edx
*(ULONG*)&Prcb->VendorString[8] = Vendor[2]; // ecx
*(ULONG*)&Prcb->VendorString[12] = 0;
/* Now check the CPU Type */
if (!strcmp((PCHAR)Prcb->VendorString, CmpIntelID))
{
return CPU_INTEL;
}
else if (!strcmp((PCHAR)Prcb->VendorString, CmpAmdID))
{
return CPU_AMD;
}
else if (!strcmp((PCHAR)Prcb->VendorString, CmpCyrixID))
{
DPRINT1("Cyrix CPUs not fully supported\n");
return 0;
}
else if (!strcmp((PCHAR)Prcb->VendorString, CmpTransmetaID))
{
DPRINT1("Transmeta CPUs not fully supported\n");
return 0;
}
else if (!strcmp((PCHAR)Prcb->VendorString, CmpCentaurID))
{
DPRINT1("VIA CPUs not fully supported\n");
return 0;
}
else if (!strcmp((PCHAR)Prcb->VendorString, CmpRiseID))
{
DPRINT1("Rise CPUs not fully supported\n");
return 0;
}
/* Invalid CPU */
return 0;
}
static void
get_cache_sizes_amd(uint max_ext_val)
{
// COMPLETEDD #253 get_cache_sizes_amd
uint cpuid_res_local[4]; /* eax, ebx, ecx, and edx registers (in that order) */
if (max_ext_val >= 0x80000005) {
#ifdef LINUX
our_cpuid((int*)cpuid_res_local, 0x80000005);
#else
__cpuid(cpuid_res_local, 0x80000005);
#endif
set_cache_size((cpuid_res_local[2]/*ecx*/ >> 24), &L1_icache_size);
set_cache_size((cpuid_res_local[3]/*edx*/ >> 24), &L1_dcache_size);
}
// init_xsave_info
void init_xsave_info()
{
int xsave_size = FXSAVE_SIZE;
uint64_t xcr0 = 0;
if(try_read_xcr0(&xcr0))
{
// CPUID function 0DH, sub-function 0
// EBX enums the size (in bytes) required by XSAVE for all the components currently set in XCR0
int cpu_info[4] = {0};
__cpuid(cpu_info, 0xD);
xsave_size = cpu_info[1];
g_xsave_enabled = 1;
}
set_xsave_info(xsave_size, (xcr0 & XFRM_YMM_BITMASK) ? 1 : 0);
}