void nrf_pwr_mgmt_run(void)
{
#if NRF_PWR_MGMT_CONFIG_FPU_SUPPORT_ENABLED
/*
* Clear FPU exceptions.
* Without this step, the FPU interrupt is marked as pending,
* preventing system from sleeping.
*/
uint32_t fpscr = __get_FPSCR();
__set_FPSCR(fpscr & ~0x9Fu);
__DMB();
NVIC_ClearPendingIRQ(FPU_IRQn);
// Assert if a critical FPU exception is signaled.
ASSERT((fpscr & 0x03) == 0);
#endif // NRF_PWR_MGMT_CONFIG_FPU_SUPPORT_ENABLED
SLEEP_LOCK();
#if NRF_PWR_MGMT_CONFIG_CPU_USAGE_MONITOR_ENABLED
uint32_t sleep_start;
uint32_t sleep_end;
uint32_t sleep_duration;
sleep_start = app_timer_cnt_get();
#endif // NRF_PWR_MGMT_CONFIG_CPU_USAGE_MONITOR_ENABLED
DEBUG_PIN_SET();
// Wait for an event.
#ifdef SOFTDEVICE_PRESENT
ret_code_t ret_code = sd_app_evt_wait();
if (ret_code == NRF_ERROR_SOFTDEVICE_NOT_ENABLED)
{
__WFE();
__SEV();
__WFE();
}
else
{
APP_ERROR_CHECK(ret_code);
}
#else
__WFE();
__SEV();
__WFE();
#endif // SOFTDEVICE_PRESENT
DEBUG_PIN_CLEAR();
#if NRF_PWR_MGMT_CONFIG_CPU_USAGE_MONITOR_ENABLED
sleep_end = app_timer_cnt_get();
UNUSED_VARIABLE(app_timer_cnt_diff_compute(sleep_end,
sleep_start,
&sleep_duration));
m_ticks_sleeping += sleep_duration;
#endif // NRF_PWR_MGMT_CONFIG_CPU_USAGE_MONITOR_ENABLED
SLEEP_RELEASE();
}
/**
* @brief Port-related initialization code.
*/
void _port_init(void) {
/* Initialization of the vector table and priority related settings.*/
SCB_VTOR = CORTEX_VTOR_INIT;
SCB_AIRCR = AIRCR_VECTKEY | AIRCR_PRIGROUP(CORTEX_PRIGROUP_INIT);
#if CORTEX_USE_FPU
{
/* Initializing the FPU context save in lazy mode.*/
SCB_FPCCR = FPCCR_ASPEN | FPCCR_LSPEN;
/* CP10 and CP11 set to full access.*/
SCB_CPACR |= 0x00F00000;
/* Enables FPU context save/restore on exception entry/exit (FPCA bit).*/
__set_CONTROL(__get_CONTROL() | 4);
/* FPSCR and FPDSCR initially zero.*/
__set_FPSCR(0);
SCB_FPDSCR = 0;
}
#endif
/* Initialization of the system vectors used by the port.*/
nvicSetSystemHandlerPriority(HANDLER_SVCALL,
CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SVCALL));
nvicSetSystemHandlerPriority(HANDLER_PENDSV,
CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_PENDSV));
nvicSetSystemHandlerPriority(HANDLER_SYSTICK,
CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SYSTICK));
}
/**
\brief Test case: TC_CoreFunc_BASEPRI
\details
- Check if __get_FPSCR and __set_FPSCR intrinsics can be used
*/
void TC_CoreFunc_FPSCR(void) {
uint32_t fpscr = __get_FPSCR();
__ISB();
__DSB();
__set_FPSCR(~fpscr);
__ISB();
__DSB();
uint32_t result = __get_FPSCR();
__set_FPSCR(fpscr);
#if (defined (__FPU_USED ) && (__FPU_USED == 1U))
ASSERT_TRUE(result != fpscr);
#else
(void)result;
#endif
}
