/*
* Initialize an SCC as a uart.
*
* Comments below reference Motorola's "MPC860 User Manual".
* The basic initialization steps are from Section 16.15.8
* of that manual.
*/
static void
cyg_hal_sccx_init_channel(struct port_info *info, int port)
{
EPPC *eppc = eppc_base();
int i;
volatile struct uart_pram *uart_pram = (volatile struct uart_pram *)((char *)eppc + info->pram);
volatile struct scc_regs *regs = (volatile struct scc_regs *)((char *)eppc + info->regs);
struct cp_bufdesc *txbd, *rxbd;
if (info->init) return;
info->init = 1;
/*
* Set up the Port pins for UART operation.
*/
switch (port) {
#if CYGNUM_HAL_QUICC_SCC1 > 0
case QUICC_CPM_SCC1:
eppc->pio_papar |= 0x03;
eppc->pio_padir &= ~0x03;
eppc->pio_paodr &= ~0x03;
/* CTS on PortC.11 */
eppc->pio_pcdir &= 0x800;
eppc->pio_pcpar &= 0x800;
eppc->pio_pcso |= 0x800;
/* RTS on PortB.19 */
eppc->pip_pbpar |= 0x1000;
eppc->pip_pbdir |= 0x1000;
break;
#endif
#if CYGNUM_HAL_QUICC_SCC2 > 0
case QUICC_CPM_SCC2:
#error FIXME
eppc->pio_papar |= 0x0C;
eppc->pio_padir &= ~0x0C;
eppc->pio_paodr &= ~0x0C;
/* CTS on PortC.11 */
eppc->pio_pcdir &= 0xC00;
eppc->pio_pcpar &= 0xC00;
eppc->pio_pcso |= 0xC00;
/* RTS on PortB.19 */
eppc->pip_pbpar |= 0x2000;
eppc->pip_pbdir |= 0x2000;
break;
#endif
#if CYGNUM_HAL_QUICC_SCC3 > 0
case QUICC_CPM_SCC3:
#if defined(CYGHWR_HAL_POWERPC_MPC8XX_850)
#if 0
// CAUTION! Enabling these bits made the port get stuck :-(
/* CTS/RTS/CD on PortC.4/5/13 */
eppc->pio_pcdir &= 0x0C04;
eppc->pio_pcpar &= 0x0C00;
// eppc->pio_pcpar |= 0x0004;
eppc->pio_pcso |= 0x0C00;
#endif
/* RxD/TxD on PortB.24/25 */
eppc->pip_pbpar |= 0x00C0;
eppc->pip_pbdir |= 0x00C0;
eppc->pip_pbodr &= ~0x00C0;
#elif defined(CYGHWR_HAL_POWERPC_MPC8XX_852T)
eppc->pio_papar |= 0x30;
eppc->pio_padir &= ~0x30;
eppc->pio_paodr &= ~0x30;
#else
#error "Cannot route SCC3 I/O"
#endif // 850T
break;
#endif // SCC3
}
// Set up baud rate generator. These are allocated from a
// pool, based on the port number and type. The allocator
// will arrange to have the selected baud rate clock steered
// to this device.
info->brg = _mpc8xx_allocate_brg(port);
*(info->brg) = 0x10000 | (UART_BIT_RATE(UART_BAUD_RATE)<<1);
/*
* Set pointers to buffer descriptors.
*/
uart_pram->rbase = _mpc8xx_allocBd(sizeof(struct cp_bufdesc)*info->Rxnum + info->Rxnum);
uart_pram->tbase = _mpc8xx_allocBd(sizeof(struct cp_bufdesc)*info->Txnum + info->Txnum);
/*
* SDMA & LCD bus request level 5
*/
eppc->dma_sdcr = 1;
/*
* Set Rx and Tx function code
*/
uart_pram->rfcr = 0x18;
uart_pram->tfcr = 0x18;
/* max receive buffer length */
uart_pram->mrblr = 1;
/* disable max_idle feature */
uart_pram->max_idl = 0;
/* no last brk char received */
uart_pram->brkln = 0;
/* no break condition occurred */
uart_pram->brkec = 0;
/* 1 break char sent on top XMIT */
uart_pram->brkcr = 1;
/* character mask */
uart_pram->rccm = 0xC0FF;
/* control characters */
for (i = 0; i < 8; i++) {
uart_pram->cc[i] = 0x8000; // Mark unused
}
/* setup RX buffer descriptors */
rxbd = (struct cp_bufdesc *)((char *)eppc + uart_pram->rbase);
info->next_rxbd = rxbd;
for (i = 0; i < info->Rxnum; i++) {
rxbd->length = 0;
rxbd->buffer = ((char *)eppc + (uart_pram->rbase+(info->Rxnum*sizeof(struct cp_bufdesc))))+i;
rxbd->ctrl = QUICC_BD_CTL_Ready | QUICC_BD_CTL_Int;
rxbd++;
}
rxbd--;
rxbd->ctrl |= QUICC_BD_CTL_Wrap;
/* setup TX buffer descriptor */
txbd = (struct cp_bufdesc *)((char *)eppc + uart_pram->tbase);
txbd->length = 0;
txbd->buffer = ((char *)eppc + (uart_pram->tbase+(info->Txnum*sizeof(struct cp_bufdesc))));
txbd->ctrl = 0x2000;
/*
* Clear any previous events. Mask interrupts.
* (Section 16.15.7.14 and 16.15.7.15)
*/
regs->scc_scce = 0xffff;
regs->scc_sccm = 1; // RX interrupts only, for ctrl-c
/*
* Set 8,n,1 characters
*/
regs->scc_psmr = (3<<12);
regs->scc_gsmr_h = 0x20; // 8bit FIFO
regs->scc_gsmr_l = 0x00028004; // 16x TxCLK, 16x RxCLK, UART
/*
* Init Rx & Tx params for SCCX
*/
eppc->cp_cr = QUICC_CPM_CR_INIT_TXRX | port | QUICC_CPM_CR_BUSY;
regs->scc_gsmr_l |= 0x30; // Enable Rx, Tx
info->irq = 0;
}
// Function to set up internal tables for device.
static void
quicc_scc_serial_init_info(quicc_sxx_serial_info *scc_chan,
volatile struct uart_pram *uart_pram,
volatile struct scc_regs *ctl,
int TxBD, int TxNUM, int TxSIZE,
cyg_uint8 *TxBUF,
int RxBD, int RxNUM, int RxSIZE,
cyg_uint8 *RxBUF,
int portAmask, int portBmask, int portCmask,
int port)
{
EPPC *eppc = eppc_base();
struct cp_bufdesc *txbd, *rxbd;
int i;
// Disable channel during setup
ctl->scc_gsmr_l = 0;
scc_chan->pram = (void *)uart_pram;
scc_chan->ctl = (void *)ctl;
// Set up baud rate generator
scc_chan->brg = _mpc8xx_allocate_brg(port);
/*
* Set up the PortA/B/C pins for UART operation.
*/
eppc->pio_papar |= portAmask;
eppc->pio_padir &= ~portAmask;
eppc->pio_paodr &= ~portAmask;
eppc->pio_pcdir &= portCmask;
eppc->pio_pcpar &= portCmask;
eppc->pio_pcso |= portCmask;
eppc->pip_pbpar |= portBmask;
eppc->pip_pbdir |= portBmask;
/*
* SDMA & LCD bus request level 5
* (Section 16.10.2.1)
*/
eppc->dma_sdcr = 1;
/*
* Set Rx and Tx function code
* (Section 16.15.4.2)
*/
uart_pram->rfcr = 0x18;
uart_pram->tfcr = 0x18;
/*
* Set pointers to buffer descriptors.
* (Sections 16.15.4.1, 16.15.7.12, and 16.15.7.13)
*/
uart_pram->rbase = RxBD;
uart_pram->tbase = TxBD;
/* tx and rx buffer descriptors */
txbd = (struct cp_bufdesc *)((char *)eppc + TxBD);
rxbd = (struct cp_bufdesc *)((char *)eppc + RxBD);
scc_chan->txbd = txbd;
scc_chan->tbase = txbd;
scc_chan->txsize = TxSIZE;
scc_chan->rxbd = rxbd;
scc_chan->rbase = rxbd;
scc_chan->rxsize = RxSIZE;
/* max receive buffer length */
uart_pram->mrblr = RxSIZE;
/* set max_idle feature - generate interrupt after 4 chars idle period */
uart_pram->max_idl = 4;
/* no last brk char received */
uart_pram->brkln = 0;
/* no break condition occurred */
uart_pram->brkec = 0;
/* 1 break char sent on top XMIT */
uart_pram->brkcr = 1;
/* character mask */
uart_pram->rccm = 0xC0FF;
/* control characters */
for (i = 0; i < 8; i++) {
uart_pram->cc[i] = 0x8000; // Mark unused
}
/* setup RX buffer descriptors */
for (i = 0; i < RxNUM; i++) {
rxbd->length = 0;
rxbd->buffer = RxBUF;
rxbd->ctrl = QUICC_BD_CTL_Ready | QUICC_BD_CTL_Int;
if (i == (RxNUM-1)) rxbd->ctrl |= QUICC_BD_CTL_Wrap; // Last buffer
RxBUF += RxSIZE;
rxbd++;
}
/* setup TX buffer descriptors */
for (i = 0; i < TxNUM; i++) {
txbd->length = 0;
txbd->buffer = TxBUF;
txbd->ctrl = 0;
if (i == (TxNUM-1)) txbd->ctrl |= QUICC_BD_CTL_Wrap; // Last buffer
TxBUF += TxSIZE;
txbd++;
}
/*
* Reset Rx & Tx params
*/
HAL_IO_BARRIER(); // Inforce I/O ordering
eppc->cp_cr = scc_chan->channel | QUICC_SMC_CMD_Go | QUICC_SMC_CMD_InitTxRx;
while (eppc->cp_cr & QUICC_SMC_CMD_Go )
continue;
/*
* Clear any previous events. Enable interrupts.
* (Section 16.15.7.14 and 16.15.7.15)
*/
HAL_IO_BARRIER(); // Inforce I/O ordering
ctl->scc_scce = 0xFFFF;
ctl->scc_sccm = (QUICC_SCCE_BSY | QUICC_SCCE_TX | QUICC_SCCE_RX);
}
/*
* Initialize SMCX as a uart.
*
* Comments below reference Motorola's "MPC860 User Manual".
* The basic initialization steps are from Section 16.15.8
* of that manual.
*/
static void
cyg_hal_smcx_init_channel(struct port_info *info, int port)
{
EPPC *eppc = eppc_base();
int i;
volatile struct smc_uart_pram *uart_pram = (volatile struct smc_uart_pram *)((char *)eppc + info->pram);
volatile struct smc_regs *regs = (volatile struct smc_regs *)((char *)eppc + info->regs);
struct cp_bufdesc *txbd, *rxbd;
if (info->init) return;
info->init = 1;
switch (port) {
#if CYGNUM_HAL_QUICC_SMC1 > 0
case QUICC_CPM_SMC1:
/*
* Set up the PortB pins for UART operation.
* Set PAR and DIR to allow SMCTXD1 and SMRXD1
* (Table 16-39)
*/
eppc->pip_pbpar |= 0xc0;
eppc->pip_pbdir &= ~0xc0;
break;
#endif
#if CYGNUM_HAL_QUICC_SMC2 > 0
case QUICC_CPM_SMC2:
/*
* Set up the PortA pins for UART operation.
* Set PAR and DIR to allow SMCTXD2 and SMRXD2
* (Table 16-39)
*/
eppc->pio_papar |= 0xc0;
eppc->pio_padir &= ~0xc0;
eppc->pio_paodr &= ~0xc0;
break;
#endif
}
// Set up baud rate generator. These are allocated from a
// pool, based on the port number and type. The allocator
// will arrange to have the selected baud rate clock steered
// to this device.
info->brg = _mpc8xx_allocate_brg(port);
*(info->brg) = 0x10000 | (UART_BIT_RATE(UART_BAUD_RATE)<<1);
/*
* Set pointers to buffer descriptors.
* (Sections 16.15.4.1, 16.15.7.12, and 16.15.7.13)
*/
uart_pram->rbase = _mpc8xx_allocBd(sizeof(struct cp_bufdesc)*info->Rxnum + info->Rxnum);
uart_pram->tbase = _mpc8xx_allocBd(sizeof(struct cp_bufdesc)*info->Txnum + info->Txnum);
/*
* SDMA & LCD bus request level 5
* (Section 16.10.2.1)
*/
eppc->dma_sdcr = 1;
/*
* Set Rx and Tx function code
* (Section 16.15.4.2)
*/
uart_pram->rfcr = 0x18;
uart_pram->tfcr = 0x18;
/* max receive buffer length */
uart_pram->mrblr = 1;
/* disable max_idle feature */
uart_pram->max_idl = 0;
/* no last brk char received */
uart_pram->brkln = 0;
/* no break condition occurred */
uart_pram->brkec = 0;
/* 1 break char sent on top XMIT */
uart_pram->brkcr = 1;
/* setup RX buffer descriptors */
rxbd = (struct cp_bufdesc *)((char *)eppc + uart_pram->rbase);
info->next_rxbd = rxbd;
for (i = 0; i < info->Rxnum; i++) {
rxbd->length = 0;
rxbd->buffer = ((char *)eppc + (uart_pram->rbase+(info->Rxnum*sizeof(struct cp_bufdesc))))+i;
rxbd->ctrl = QUICC_BD_CTL_Ready | QUICC_BD_CTL_Int;
rxbd++;
}
rxbd--;
rxbd->ctrl |= QUICC_BD_CTL_Wrap;
/* setup TX buffer descriptor */
txbd = (struct cp_bufdesc *)((char *)eppc + uart_pram->tbase);
txbd->length = 1;
txbd->buffer = ((char *)eppc + (uart_pram->tbase+(info->Txnum*sizeof(struct cp_bufdesc))));
txbd->ctrl = 0x2000;
/*
* Clear any previous events. Mask interrupts.
* (Section 16.15.7.14 and 16.15.7.15)
*/
regs->smc_smce = 0xff;
regs->smc_smcm = 1; // RX interrupts only, for ctrl-c
/*
* Set 8,n,1 characters, then also enable rx and tx.
* (Section 16.15.7.11)
*/
regs->smc_smcmr = 0x4820;
regs->smc_smcmr = 0x4823;
/*
* Init Rx & Tx params for SMCx
*/
eppc->cp_cr = QUICC_CPM_CR_INIT_TXRX | port | QUICC_CPM_CR_BUSY;
info->irq = 0; // Interrupts not enabled
}
