/** * omap3_noncore_dpll_enable - instruct a DPLL to enter bypass or lock mode * @clk: pointer to a DPLL struct clk * * Instructs a non-CORE DPLL to enable, e.g., to enter bypass or lock. * The choice of modes depends on the DPLL's programmed rate: if it is * the same as the DPLL's parent clock, it will enter bypass; * otherwise, it will enter lock. This code will wait for the DPLL to * indicate readiness before returning, unless the DPLL takes too long * to enter the target state. Intended to be used as the struct clk's * enable function. If DPLL3 was passed in, or the DPLL does not * support low-power stop, or if the DPLL took too long to enter * bypass or lock, return -EINVAL; otherwise, return 0. */ static void omap3_noncore_dpll_disable(struct clk *clk) { if (clk == &dpll3_ck) return; _omap3_noncore_dpll_stop(clk); }
/** * omap3_noncore_dpll_disable - instruct a DPLL to enter low-power stop * @clk: pointer to a DPLL struct clk * * Instructs a non-CORE DPLL to enter low-power stop. This function is * intended for use in struct clkops. No return value. */ void omap3_noncore_dpll_disable(struct clk_hw *hw) { struct clk_hw_omap *clk = to_clk_hw_omap(hw); _omap3_noncore_dpll_stop(clk); if (clk->clkdm) clkdm_clk_disable(clk->clkdm, hw->clk); }
/** * omap3_noncore_dpll_disable - instruct a DPLL to enter low-power stop * @clk: pointer to a DPLL struct clk * * Instructs a non-CORE DPLL to enter low-power stop. This function is * intended for use in struct clkops. No return value. */ void omap3_noncore_dpll_disable(struct clk *clk) { _omap3_noncore_dpll_stop(clk); }