Example #1
0
void sb700_mci(device_t dev, int enabled)
{
        device_t sm_dev;
        int index;
	int function;

	_pci_break_tag(dev, NULL, NULL, &function);
        index = function - 5;
        sm_dev = _pci_make_tag(0, 0x14, 0);
        set_pmio_enable_bits(sm_dev, 0x59, 1 << index, (enabled ? 1 : 0) << index);
}
Example #2
0
void
_pci_tagprintf (pcitag_t tag, const char *fmt, ...)
{
    va_list arg;
    int bus, device, function;

    _pci_break_tag (tag, &bus, &device, &function); 
    print_bdf (bus, device, function);

    va_start(arg, fmt);
    VPRINTF (fmt, arg);
    va_end(arg);
}
Example #3
0
void rs780_enable(device_t dev)
{
    device_t nb_dev, sb_dev;
    int dev_ind;

    nb_dev = _pci_make_tag(0, 0, 0);
    sb_dev = _pci_make_tag(0, 8, 0);

    _pci_break_tag(dev, NULL, &dev_ind, NULL);

    switch(dev_ind) {
    case 0:
        printk_info("enable_pcie_bar3\n");
        enable_pcie_bar3(nb_dev);       /* PCIEMiscInit */
        printk_info("config_gpp_core\n");
        config_gpp_core(nb_dev, sb_dev);
        printk_info("rs780_gpp_sb_init\n");
        rs780_gpp_sb_init(nb_dev, sb_dev, 8);
        /* set SB payload size: 64byte */
        printk_info("set sb payload size:64byte\n");
        set_pcie_enable_bits(nb_dev, 0x10 | PCIE_CORE_INDEX_GPPSB, 3 << 11, 2 << 11);

        /* Bus0Dev0Fun1Clock control init, we have to do it here, for dev0 Fun1 doesn't have a vendor or device ID */
        //rs780_config_misc_clk(nb_dev);
        {   /* BTDC: NBPOR_InitPOR function. */
            u8 temp8;
            u16 temp16;
            u32 temp32;

            /* BTDC: Program NB PCI table. */
            printk_info("Program NB PCI table\n");
            temp16 = pci_read_config16(nb_dev, 0x04);
            printk_debug("BTDC: NB_PCI_REG04 = %x.\n", temp16);
            temp32 = pci_read_config32(nb_dev, 0x84);
            printk_debug("BTDC: NB_PCI_REG84 = %x.\n", temp32);

            pci_write_config8(nb_dev, 0x4c, 0x42);
            temp8 = pci_read_config8(nb_dev, 0x4e);
            temp8 |= 0x05;
            pci_write_config8(nb_dev, 0x4e, temp8);
            temp32 = pci_read_config32(nb_dev, 0x4c);
            printk_debug("BTDC: NB_PCI_REG4C = %x.\n", temp32);
            /* BTDC: disable GFX debug. */
            printk_info("disable gfx debug\n");
            temp8 = pci_read_config8(nb_dev, 0x8d);
            temp8 &= ~(1<<1);
            pci_write_config8(nb_dev, 0x8d, temp8);
            /* BTDC: set temporary NB TOM to 0x40000000. */
            //printk_info("set temporary NB TOM to 0xf0000000\n");
            //pci_write_config32(nb_dev, 0x90, 0x40000000);
            //pci_write_config32(nb_dev, 0x90, 0xf0000000);
            printk_info("set temporary NB TOM to 0xffffffff\n");
            pci_write_config32(nb_dev, 0x90, 0xffffffff);
            /* BTDC: Program NB HTIU table. */
            printk_info("Program NB HTIU table\n");
            set_htiu_enable_bits(nb_dev, 0x05, 1<<10 | 1<<9, 1<<10|1<<9);
            set_htiu_enable_bits(nb_dev, 0x06, 1, 0x4203a202);
            set_htiu_enable_bits(nb_dev, 0x07, 1<<1 | 1<<2, 0x8001);
            set_htiu_enable_bits(nb_dev, 0x15, 0, 1<<31 | 1<<30 | 1<<27);
            set_htiu_enable_bits(nb_dev, 0x1c, 0, 0xfffe0000);
            set_htiu_enable_bits(nb_dev, 0x4b, 1<<11, 1<<11);
            set_htiu_enable_bits(nb_dev, 0x0c, 0x3f, 1 | 1<<3);
            set_htiu_enable_bits(nb_dev, 0x17, 1<<1 | 1<<27, 1<<1);
            set_htiu_enable_bits(nb_dev, 0x17, 0, 1<<30);
            set_htiu_enable_bits(nb_dev, 0x19, 0xfffff+(1<<31), 0x186a0+(1<<31));
            set_htiu_enable_bits(nb_dev, 0x16, 0x3f<<10, 0x7<<10);
            set_htiu_enable_bits(nb_dev, 0x23, 0, 1<<28);
            /* BTDC: Program NB MISC table. */
            printk_info("set NB MISC table\n");
            set_nbmisc_enable_bits(nb_dev, 0x0b, 0xffff, 0x00000180);
            set_nbmisc_enable_bits(nb_dev, 0x00, 0xffff, 0x00000106);
            set_nbmisc_enable_bits(nb_dev, 0x51, 0xffffffff, 0x00100100);
            set_nbmisc_enable_bits(nb_dev, 0x53, 0xffffffff, 0x00100100);
            set_nbmisc_enable_bits(nb_dev, 0x55, 0xffffffff, 0x00100100);
            set_nbmisc_enable_bits(nb_dev, 0x57, 0xffffffff, 0x00100100);
            set_nbmisc_enable_bits(nb_dev, 0x59, 0xffffffff, 0x00100100);
            set_nbmisc_enable_bits(nb_dev, 0x5b, 0xffffffff, 0x00100100);
            set_nbmisc_enable_bits(nb_dev, 0x5d, 0xffffffff, 0x00100100);
            set_nbmisc_enable_bits(nb_dev, 0x5f, 0xffffffff, 0x00100100);
            set_nbmisc_enable_bits(nb_dev, 0x20, 1<<1, 0);
            set_nbmisc_enable_bits(nb_dev, 0x37, 1<<11|1<<12|1<<13|1<<26, 0);
            set_nbmisc_enable_bits(nb_dev, 0x68, 1<<5|1<<6, 1<<5);
            set_nbmisc_enable_bits(nb_dev, 0x6b, 1<<22, 1<<10);
            set_nbmisc_enable_bits(nb_dev, 0x67, 1<<26, 1<<14|1<<10);
            set_nbmisc_enable_bits(nb_dev, 0x24, 1<<28|1<<26|1<<25|1<<16, 1<<29|1<<25);
            set_nbmisc_enable_bits(nb_dev, 0x38, 1<<24|1<<25, 1<<24);
            set_nbmisc_enable_bits(nb_dev, 0x36, 1<<29, 1<<29|1<<28);
            set_nbmisc_enable_bits(nb_dev, 0x0c, 0, 1<<13);
            set_nbmisc_enable_bits(nb_dev, 0x34, 1<<22, 1<<10);
            set_nbmisc_enable_bits(nb_dev, 0x39, 1<<10, 1<<30);
            set_nbmisc_enable_bits(nb_dev, 0x22, 1<<3, 0);
            set_nbmisc_enable_bits(nb_dev, 0x68, 1<<19, 0);
            set_nbmisc_enable_bits(nb_dev, 0x24, 1<<16|1<<17, 1<<17);
            set_nbmisc_enable_bits(nb_dev, 0x6a, 1<<22|1<<23, 1<<17|1<<23);
            set_nbmisc_enable_bits(nb_dev, 0x35, 1<<21|1<<22, 1<<22);
            set_nbmisc_enable_bits(nb_dev, 0x01, 0xffffffff, 0x48);
            /* BTDC: the last two step. */
            set_nbmisc_enable_bits(nb_dev, 0x01, 1<<8, 1<<8);
            set_htiu_enable_bits(nb_dev, 0x2d, 1<<6|1<<4, 1<<6|1<<4);
        }
        break;
    case 1: /* bus0, dev1, APC. */
        printk_info("Bus-0, Dev-1, Fun-0.\n");
        rs780_internal_gfx_enable(nb_dev,dev);
        break;
    case 2:
    case 3:
        set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << dev_ind,
                               (1 ? 0 : 1) << dev_ind);
        rs780_gfx_init(nb_dev, dev, dev_ind);
        break;
    case 4:		/* bus0, dev4-7, four GPP */
    case 5:
    case 6:
    case 7:
        enable_pcie_bar3(nb_dev);	/* PCIEMiscInit */
        set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << dev_ind,
                               (1 ? 0 : 1) << dev_ind);
        rs780_gpp_sb_init(nb_dev, dev, dev_ind);
        break;
    case 8:		/* bus0, dev8, SB */
        set_nbmisc_enable_bits(nb_dev, 0x00, 1 << 6,
                               (1 ? 0 : 1) << dev_ind);
        rs780_gpp_sb_init(nb_dev, dev, dev_ind);
        disable_pcie_bar3(nb_dev);
        break;
    case 9:		/* bus 0, dev 9,10, GPP */
    case 10:
        enable_pcie_bar3(nb_dev);	/* PCIEMiscInit */
        set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << (7 + dev_ind),
                               (1 ? 0 : 1) << (7 + dev_ind));
        rs780_gpp_sb_init(nb_dev, dev, dev_ind);
        break;
    default:
        printk_debug("unknown dev: %s\n", dev_ind);
    }
}