rtems_device_driver sh_sci_open(
rtems_device_major_number major,
rtems_device_minor_number minor,
void * arg )
{
uint8_t temp8;
/* check for valid minor number */
if(( minor > ( SCI_MINOR_DEVICES -1 )) || ( minor < 0 ))
{
return RTEMS_INVALID_NUMBER;
}
/* device already opened */
if ( sci_device[minor].opened > 0 )
{
sci_device[minor].opened++ ;
return RTEMS_SUCCESSFUL ;
}
_sci_init( minor );
if (minor == 0) {
temp8 = read8(sci_device[minor].addr + SCI_SCR);
temp8 &= ~(SCI_TE | SCI_RE) ;
write8(temp8, sci_device[minor].addr + SCI_SCR); /* Clear SCR */
_sci_set_cflags( &sci_device[minor], sci_device[minor].cflags );
/* FIXME: Should be one bit delay */
CPU_delay(50000); /* microseconds */
temp8 |= SCI_RE | SCI_TE;
write8(temp8, sci_device[minor].addr + SCI_SCR); /* Enable clock output */
} else {
temp8 = read8(sci_device[minor].addr + SCI_SCR);
temp8 &= ~(SCI_TE | SCI_RE) ;
write8(temp8, sci_device[minor].addr + SCI_SCR); /* Clear SCR */
_sci_set_cflags( &sci_device[minor], sci_device[minor].cflags );
/* FIXME: Should be one bit delay */
CPU_delay(50000); /* microseconds */
temp8 |= SCI_RE | SCI_TE;
write8(temp8, sci_device[minor].addr + SCI_SCR); /* Enable clock output */
}
sci_device[minor].opened++ ;
return RTEMS_SUCCESSFUL ;
}
/*
* Termios set attributes
*/
static int _sh_sci_set_attributes( int minor, const struct termios *t)
{
return _sci_set_cflags( &sci_device[ minor ], t->c_cflag);
}
rtems_device_driver sh_sci_open(
rtems_device_major_number major,
rtems_device_minor_number minor,
void * arg )
{
uint8_t temp8;
uint16_t temp16;
unsigned a;
/* check for valid minor number */
if (( minor > ( SCI_MINOR_DEVICES -1 )) || ( minor < 0 ))
{
return RTEMS_INVALID_NUMBER;
}
/* device already opened */
if ( sci_device[minor].opened > 0 )
{
sci_device[minor].opened++;
return RTEMS_SUCCESSFUL;
}
/* set PFC registers to enable I/O pins */
if ((minor == 0)) {
temp16 = read16(PFC_PACRL2); /* disable SCK0, DMA, IRQ */
temp16 &= ~(PA2MD1 | PA2MD0);
temp16 |= (PA_TXD0 | PA_RXD0); /* enable pins for Tx0, Rx0 */
write16(temp16, PFC_PACRL2);
} else if (minor == 1) {
temp16 = read16(PFC_PACRL2); /* disable SCK1, DMA, IRQ */
temp16 &= ~(PA5MD1 | PA5MD0);
temp16 |= (PA_TXD1 | PA_RXD1); /* enable pins for Tx1, Rx1 */
write16(temp16, PFC_PACRL2);
} /* add other devices and pins as req'd. */
/* set up SCI registers */
write8(0x00, sci_device[minor].addr + SCI_SCR); /* Clear SCR */
/* set SMR and BRR */
_sci_set_cflags( &sci_device[minor], sci_device[minor].cflags );
for (a=0; a < 10000L; a++) { /* Delay */
__asm__ volatile ("nop");
}
write8((SCI_RE | SCI_TE), /* enable async. Tx and Rx */
sci_device[minor].addr + SCI_SCR);
/* clear error flags */
temp8 = read8(sci_device[minor].addr + SCI_SSR);
while (temp8 & (SCI_RDRF | SCI_ORER | SCI_FER | SCI_PER)) {
temp8 = read8(sci_device[minor].addr + SCI_RDR); /* flush input */
temp8 = read8(sci_device[minor].addr + SCI_SSR); /* clear some flags */
write8(temp8 & ~(SCI_RDRF | SCI_ORER | SCI_FER | SCI_PER),
sci_device[minor].addr + SCI_SSR);
temp8 = read8(sci_device[minor].addr + SCI_SSR); /* check if everything is OK */
}
/* Clear RDRF flag */
write8(0x00, sci_device[minor].addr + SCI_TDR); /* force output */
/* Clear the TDRE bit */
temp8 = read8(sci_device[minor].addr + SCI_SSR) & ~SCI_TDRE;
write8(temp8, sci_device[minor].addr + SCI_SSR);
/* add interrupt setup if required */
sci_device[minor].opened++;
return RTEMS_SUCCESSFUL;
}
