/* * * Parameters * padapter * pslv power state level, only could be PS_STATE_S0 ~ PS_STATE_S4 * */ void rtw_set_rpwm(PADAPTER padapter, u8 pslv) { u8 rpwm; struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv; _func_enter_; pslv = PS_STATE(pslv); if (_TRUE == padapter->pwrctrlpriv.btcoex_rfon) { if (pslv < PS_STATE_S4) pslv = PS_STATE_S3; if (pwrpriv->rpwm == pslv) { struct reportpwrstate_parm report; report.state = PS_STATE_S3; #ifdef CONFIG_LPS_LCLK //cpwm_int_hdl(padapter, &report); _set_workitem(&padapter->pwrctrlpriv.cpwm_event); #endif return; } } #ifdef CONFIG_LPS_RPWM_TIMER if (pwrpriv->brpwmtimeout == _TRUE) { DBG_871X("%s: RPWM timeout, force to set RPWM(0x%02X) again!\n", __FUNCTION__, pslv); } else #endif // CONFIG_LPS_RPWM_TIMER { if ( (pwrpriv->rpwm == pslv) #ifdef CONFIG_LPS_LCLK || ((pwrpriv->rpwm >= PS_STATE_S2)&&(pslv >= PS_STATE_S2)) #endif ) { RT_TRACE(_module_rtl871x_pwrctrl_c_,_drv_err_, ("%s: Already set rpwm[0x%02X], new=0x%02X!\n", __FUNCTION__, pwrpriv->rpwm, pslv)); return; } } if ((padapter->bSurpriseRemoved == _TRUE) || (padapter->hw_init_completed == _FALSE)) { RT_TRACE(_module_rtl871x_pwrctrl_c_, _drv_err_, ("%s: SurpriseRemoved(%d) hw_init_completed(%d)\n", __FUNCTION__, padapter->bSurpriseRemoved, padapter->hw_init_completed)); pwrpriv->cpwm = PS_STATE_S4; return; } if (padapter->bDriverStopped == _TRUE) { RT_TRACE(_module_rtl871x_pwrctrl_c_, _drv_err_, ("%s: change power state(0x%02X) when DriverStopped\n", __FUNCTION__, pslv)); if (pslv < PS_STATE_S2) { RT_TRACE(_module_rtl871x_pwrctrl_c_, _drv_err_, ("%s: Reject to enter PS_STATE(0x%02X) lower than S2 when DriverStopped!!\n", __FUNCTION__, pslv)); return; } } rpwm = pslv | pwrpriv->tog; #ifdef CONFIG_LPS_LCLK // only when from PS_STATE S0/S1 to S2 and higher needs ACK if ((pwrpriv->cpwm < PS_STATE_S2) && (pslv >= PS_STATE_S2)) rpwm |= PS_ACK; #endif RT_TRACE(_module_rtl871x_pwrctrl_c_, _drv_notice_, ("rtw_set_rpwm: rpwm=0x%02x cpwm=0x%02x\n", rpwm, pwrpriv->cpwm)); pwrpriv->rpwm = pslv; #ifdef CONFIG_LPS_RPWM_TIMER if (rpwm & PS_ACK) _set_timer(&pwrpriv->pwr_rpwm_timer, LPS_RPWM_WAIT_MS); #endif // CONFIG_LPS_RPWM_TIMER rtw_hal_set_hwreg(padapter, HW_VAR_SET_RPWM, (u8 *)(&rpwm)); pwrpriv->tog += 0x80; if (_TRUE == padapter->pwrctrlpriv.btcoex_rfon) { struct reportpwrstate_parm report; report.state = pslv; #ifdef CONFIG_LPS_LCLK //cpwm_int_hdl(padapter, &report); _set_workitem(&padapter->pwrctrlpriv.cpwm_event); #endif } else { #ifdef CONFIG_LPS_LCLK // No LPS 32K, No Ack if (!(rpwm & PS_ACK)) #endif { pwrpriv->cpwm = pslv; } } _func_exit_; }
void interrupt_handler_8812au(_adapter *padapter,u16 pkt_len,u8 *pbuf) { HAL_DATA_TYPE *pHalData=GET_HAL_DATA(padapter); struct reportpwrstate_parm pwr_rpt; if ( pkt_len != INTERRUPT_MSG_FORMAT_LEN ) { DBG_8192C("%s Invalid interrupt content length (%d)!\n", __FUNCTION__, pkt_len); return ; } // HISR _rtw_memcpy(&(pHalData->IntArray[0]), &(pbuf[USB_INTR_CONTENT_HISR_OFFSET]), 4); _rtw_memcpy(&(pHalData->IntArray[1]), &(pbuf[USB_INTR_CONTENT_HISRE_OFFSET]), 4); #if 0 //DBG { u32 hisr=0 ,hisr_ex=0; _rtw_memcpy(&hisr,&(pHalData->IntArray[0]),4); hisr = le32_to_cpu(hisr); _rtw_memcpy(&hisr_ex,&(pHalData->IntArray[1]),4); hisr_ex = le32_to_cpu(hisr_ex); if((hisr != 0) || (hisr_ex!=0)) DBG_871X("===> %s hisr:0x%08x ,hisr_ex:0x%08x \n",__FUNCTION__,hisr,hisr_ex); } #endif #ifdef CONFIG_LPS_LCLK if( pHalData->IntArray[0] & IMR_CPWM_88E ) { _rtw_memcpy(&pwr_rpt.state, &(pbuf[USB_INTR_CONTENT_CPWM1_OFFSET]), 1); //_rtw_memcpy(&pwr_rpt.state2, &(pbuf[USB_INTR_CONTENT_CPWM2_OFFSET]), 1); //88e's cpwm value only change BIT0, so driver need to add PS_STATE_S2 for LPS flow. pwr_rpt.state |= PS_STATE_S2; _set_workitem(&(adapter_to_pwrctl(padapter)->cpwm_event)); } #endif//CONFIG_LPS_LCLK #ifdef CONFIG_INTERRUPT_BASED_TXBCN #ifdef CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT if (pHalData->IntArray[0] & IMR_BCNDMAINT0_88E) #endif #ifdef CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR if (pHalData->IntArray[0] & (IMR_TBDER_88E|IMR_TBDOK_88E)) #endif { struct mlme_priv *pmlmepriv = &padapter->mlmepriv; #if 0 if(pHalData->IntArray[0] & IMR_BCNDMAINT0_88E) DBG_8192C("%s: HISR_BCNERLY_INT\n", __func__); if(pHalData->IntArray[0] & IMR_TBDOK_88E) DBG_8192C("%s: HISR_TXBCNOK\n", __func__); if(pHalData->IntArray[0] & IMR_TBDER_88E) DBG_8192C("%s: HISR_TXBCNERR\n", __func__); #endif if(check_fwstate(pmlmepriv, WIFI_AP_STATE)) { //send_beacon(padapter); if(pmlmepriv->update_bcn == _TRUE) { //tx_beacon_hdl(padapter, NULL); set_tx_beacon_cmd(padapter); } } #ifdef CONFIG_CONCURRENT_MODE if(check_buddy_fwstate(padapter, WIFI_AP_STATE)) { //send_beacon(padapter); if(padapter->pbuddy_adapter->mlmepriv.update_bcn == _TRUE) { //tx_beacon_hdl(padapter, NULL); set_tx_beacon_cmd(padapter->pbuddy_adapter); } } #endif } #endif //CONFIG_INTERRUPT_BASED_TXBCN #ifdef DBG_CONFIG_ERROR_DETECT_INT if( pHalData->IntArray[1] & IMR_TXERR_88E ) DBG_871X("===> %s Tx Error Flag Interrupt Status \n",__FUNCTION__); if( pHalData->IntArray[1] & IMR_RXERR_88E ) DBG_871X("===> %s Rx Error Flag INT Status \n",__FUNCTION__); if( pHalData->IntArray[1] & IMR_TXFOVW_88E ) DBG_871X("===> %s Transmit FIFO Overflow \n",__FUNCTION__); if( pHalData->IntArray[1] & IMR_RXFOVW_88E ) DBG_871X("===> %s Receive FIFO Overflow \n",__FUNCTION__); #endif//DBG_CONFIG_ERROR_DETECT_INT // C2H Event if(pbuf[0]!= 0){ _rtw_memcpy(&(pHalData->C2hArray[0]), &(pbuf[USB_INTR_CONTENT_C2H_OFFSET]), 16); //rtw_c2h_wk_cmd(padapter); to do.. } }
void sd_int_dpc(PADAPTER padapter) { HAL_DATA_TYPE *phal; struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); struct intf_hdl * pintfhdl=&padapter->iopriv.intf; phal = GET_HAL_DATA(padapter); if (phal->sdio_hisr & SDIO_HISR_CPWM1) { struct reportpwrstate_parm report; #ifdef CONFIG_LPS_RPWM_TIMER u8 bcancelled; _cancel_timer(&(adapter_to_pwrctl(padapter)->pwr_rpwm_timer), &bcancelled); #endif // CONFIG_LPS_RPWM_TIMER _sdio_local_read(padapter, SDIO_REG_HCPWM1, 1, &report.state); #ifdef CONFIG_LPS_LCLK //cpwm_int_hdl(padapter, &report); _set_workitem(&(adapter_to_pwrctl(padapter)->cpwm_event)); #endif } if (phal->sdio_hisr & SDIO_HISR_TXERR) { u8 *status; u32 addr; status = rtw_malloc(4); if (status) { addr = REG_TXDMA_STATUS; HalSdioGetCmdAddr8723ASdio(padapter, WLAN_IOREG_DEVICE_ID, addr, &addr); _sd_read(pintfhdl, addr, 4, status); _sd_write(pintfhdl, addr, 4, status); DBG_8192C("%s: SDIO_HISR_TXERR (0x%08x)\n", __func__, le32_to_cpu(*(u32*)status)); rtw_mfree(status, 4); } else { DBG_8192C("%s: SDIO_HISR_TXERR, but can't allocate memory to read status!\n", __func__); } } if (phal->sdio_hisr & SDIO_HISR_TXBCNOK) { DBG_8192C("%s: SDIO_HISR_TXBCNOK\n", __func__); } if (phal->sdio_hisr & SDIO_HISR_TXBCNERR) { DBG_8192C("%s: SDIO_HISR_TXBCNERR\n", __func__); } if (phal->sdio_hisr & SDIO_HISR_C2HCMD) { struct c2h_evt_hdr *c2h_evt; if ((c2h_evt = (struct c2h_evt_hdr *)rtw_zmalloc(16)) != NULL) { if (c2h_evt_read(padapter, (u8 *)c2h_evt) == _SUCCESS) { if (c2h_id_filter_ccx_8723a(c2h_evt->id)) { /* Handle CCX report here */ rtw_hal_c2h_handler(padapter, c2h_evt); rtw_mfree((u8*)c2h_evt, 16); } else { rtw_c2h_wk_cmd(padapter, (u8 *)c2h_evt); } } else { rtw_mfree((u8*)c2h_evt, 16); } } else { /* Error handling for malloc fail */ if (rtw_cbuf_push(padapter->evtpriv.c2h_queue, (void*)NULL) != _SUCCESS) DBG_871X("%s rtw_cbuf_push fail\n", __func__); _set_workitem(&padapter->evtpriv.c2h_wk); } } if (phal->sdio_hisr & SDIO_HISR_RX_REQUEST) { struct recv_buf *precvbuf; u16 val=0; // DBG_8192C("%s: RX Request, size=%d\n", __func__, phal->SdioRxFIFOSize); phal->sdio_hisr ^= SDIO_HISR_RX_REQUEST; do{ if (phal->SdioRxFIFOSize == 0) { _sdio_local_read(padapter, SDIO_REG_RX0_REQ_LEN, 2, (u8*)&val); phal->SdioRxFIFOSize = le16_to_cpu(val); DBG_8192C("%s: RX_REQUEST, read RXFIFOsize again size=%d\n", __func__, phal->SdioRxFIFOSize); } if (phal->SdioRxFIFOSize != 0) { #ifdef CONFIG_MAC_LOOPBACK_DRIVER sd_recv_loopback(padapter, phal->SdioRxFIFOSize); #else precvbuf = sd_recv_rxfifo(padapter, phal->SdioRxFIFOSize); if (precvbuf) sd_rxhandler(padapter, precvbuf); else break; #endif } _sdio_local_read(padapter, SDIO_REG_RX0_REQ_LEN, 2, (u8*)&val); phal->SdioRxFIFOSize = le16_to_cpu(val); }while(phal->SdioRxFIFOSize !=0); } }
void sd_int_dpc(PADAPTER padapter) { HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); if (pHalData->sdio_hisr & SDIO_HISR_CPWM1) { struct reportpwrstate_parm report; _sdio_local_read(padapter, SDIO_REG_HCPWM1, 1, &report.state); #ifdef CONFIG_LPS_LCLK //88e's cpwm value only change BIT0, so driver need to add PS_STATE_S2 for LPS flow. //modify by Thomas. 2012/4/2. #ifdef CONFIG_EXT_CLK //for sprd if(report.state & BIT(4)) //indicate FW entering 32k { u8 chk_cnt = 0; do{ if(_sdio_read8(padapter, 0x90)&BIT(0))//FW in 32k already { struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv; if(pwrpriv->rpwm < PS_STATE_S2) { //DBG_871X("disable ext clk when FW in LPS-32K already!\n"); EnableGpio5ClockReq(padapter, _TRUE, 0); } break; } chk_cnt++; }while(chk_cnt<10); if(chk_cnt==10) { DBG_871X("polling fw in 32k already, fail!\n"); } } else //indicate fw leaving 32K #endif //CONFIG_EXT_CLK { report.state |= PS_STATE_S2; //cpwm_int_hdl(padapter, &report); _set_workitem(&padapter->pwrctrlpriv.cpwm_event); } #endif } #ifdef CONFIG_WOWLAN if (pHalData->sdio_hisr & SDIO_HISR_CPWM2) { u32 value; value = rtw_read32(padapter, SDIO_LOCAL_BASE+SDIO_REG_HISR); DBG_871X_LEVEL(_drv_always_, "Reset SDIO HISR(0x%08x) original:0x%08x\n", SDIO_LOCAL_BASE+SDIO_REG_HISR, value); value |= BIT19; rtw_write32(padapter, SDIO_LOCAL_BASE+SDIO_REG_HISR, value); value = rtw_read8(padapter, SDIO_LOCAL_BASE+SDIO_REG_HIMR+2); DBG_871X_LEVEL(_drv_always_, "Reset SDIO HIMR CPWM2(0x%08x) original:0x%02x\n", SDIO_LOCAL_BASE+SDIO_REG_HIMR + 2, value); } #endif if (pHalData->sdio_hisr & SDIO_HISR_TXERR) { u8 *status; u32 addr; status = _rtw_malloc(4); if (status) { addr = REG_TXDMA_STATUS; HalSdioGetCmdAddr8723ASdio(padapter, WLAN_IOREG_DEVICE_ID, addr, &addr); _sd_read(&adapter_to_dvobj(padapter)->intf_data, addr, 4, status); _sd_write(&adapter_to_dvobj(padapter)->intf_data, addr, 4, status); DBG_8192C("%s: SDIO_HISR_TXERR (0x%08x)\n", __func__, le32_to_cpu(*(u32*)status)); _rtw_mfree(status, 4); } else { DBG_8192C("%s: SDIO_HISR_TXERR, but can't allocate memory to read status!\n", __func__); } } #ifdef CONFIG_INTERRUPT_BASED_TXBCN #ifdef CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT if (pHalData->sdio_hisr & SDIO_HISR_BCNERLY_INT) #endif #ifdef CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR if (pHalData->sdio_hisr & (SDIO_HISR_TXBCNOK|SDIO_HISR_TXBCNERR)) #endif { struct mlme_priv *pmlmepriv = &padapter->mlmepriv; #if 0 //for debug if (pHalData->sdio_hisr & SDIO_HISR_BCNERLY_INT) DBG_8192C("%s: SDIO_HISR_BCNERLY_INT\n", __func__); if (pHalData->sdio_hisr & SDIO_HISR_TXBCNOK) DBG_8192C("%s: SDIO_HISR_TXBCNOK\n", __func__); if (pHalData->sdio_hisr & SDIO_HISR_TXBCNERR) DBG_8192C("%s: SDIO_HISR_TXBCNERR\n", __func__); #endif if(check_fwstate(pmlmepriv, WIFI_AP_STATE)) { //send_beacon(padapter); if(pmlmepriv->update_bcn == _TRUE) { //tx_beacon_hdl(padapter, NULL); set_tx_beacon_cmd(padapter); } } #ifdef CONFIG_CONCURRENT_MODE if(check_buddy_fwstate(padapter, WIFI_AP_STATE)) { //send_beacon(padapter); if(padapter->pbuddy_adapter->mlmepriv.update_bcn == _TRUE) { //tx_beacon_hdl(padapter, NULL); set_tx_beacon_cmd(padapter->pbuddy_adapter); } } #endif } #endif //CONFIG_INTERRUPT_BASED_TXBCN #ifdef CONFIG_EXT_CLK if (pHalData->sdio_hisr & SDIO_HISR_BCNERLY_INT) { struct mlme_priv *pmlmepriv = &padapter->mlmepriv; if(check_fwstate(pmlmepriv, _FW_LINKED) && check_fwstate(pmlmepriv, WIFI_STATION_STATE)) { //DBG_8192C("BCNERLY_INT for enabling ext clk\n"); EnableGpio5ClockReq(padapter, _TRUE, 1); } } #endif //CONFIG_EXT_CLK if (pHalData->sdio_hisr & SDIO_HISR_C2HCMD) { DBG_8192C("%s: C2H Command\n", __func__); } if (pHalData->sdio_hisr & SDIO_HISR_RX_REQUEST) { struct recv_buf *precvbuf; //DBG_8192C("%s: RX Request, size=%d\n", __func__, phal->SdioRxFIFOSize); pHalData->sdio_hisr ^= SDIO_HISR_RX_REQUEST; #ifdef CONFIG_MAC_LOOPBACK_DRIVER sd_recv_loopback(padapter, pHalData->SdioRxFIFOSize); #else do { //Sometimes rx length will be zero. driver need to use cmd53 read again. if(pHalData->SdioRxFIFOSize == 0) { u8 data[4]; _sdio_local_read(padapter, SDIO_REG_RX0_REQ_LEN, 4, data); pHalData->SdioRxFIFOSize = le16_to_cpu(*(u16*)data); } if(pHalData->SdioRxFIFOSize) { precvbuf = sd_recv_rxfifo(padapter, pHalData->SdioRxFIFOSize); pHalData->SdioRxFIFOSize = 0; if (precvbuf) sd_rxhandler(padapter, precvbuf); else break; } else break; #ifdef CONFIG_SDIO_DISABLE_RXFIFO_POLLING_LOOP } while (0); #else } while (1); #endif #endif }
void _off_ch_timer_hdl(void *FunctionContext) { struct sta_info *ptdls_sta = (struct sta_info *)FunctionContext; _set_workitem(&ptdls_sta->off_ch_workitem); }
// 1: write RCR DATA BIT // 2: issue peer traffic indication // 3: go back to the channel linked with AP, terminating channel switch procedure // 4: init channel sensing, receive all data and mgnt frame // 5: channel sensing and report candidate channel // 6: first time set channel to off channel // 7: go back tp the channel linked with AP when set base channel as target channel void TDLS_option_workitem_callback(struct work_struct *work) { struct sta_info *ptdls_sta = container_of(work, struct sta_info, option_workitem); _adapter *padapter = ptdls_sta->padapter; struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info; u32 bit_6=1<<6, bit_7=1<<7, bit_4=1<<4; u8 survey_channel, i, min; switch(ptdls_sta->option){ case 1: //As long as TDLS handshake success, we should set RCR_CBSSID_DATA bit to 0 //such we can receive all kinds of data frames. rtw_write32(padapter, 0x0608, rtw_read32(padapter, 0x0608)&(~bit_6)); DBG_8192C("wirte 0x0608, set bit6 off\n"); break; case 2: issue_tdls_peer_traffic_indication(padapter, ptdls_sta); break; case 3: _cancel_timer_ex(&ptdls_sta->base_ch_timer); _cancel_timer_ex(&ptdls_sta->off_ch_timer); SelectChannel(padapter, pmlmeext->cur_channel); ptdls_sta->state &= ~(TDLS_CH_SWITCH_ON_STATE | TDLS_PEER_AT_OFF_STATE | TDLS_AT_OFF_CH_STATE); DBG_8192C("go back to base channel\n "); issue_nulldata(padapter, 0); break; case 4: rtw_write32(padapter, 0x0608, rtw_read32(padapter, 0x0608)&(~bit_6)&(~bit_7)); rtw_write16(padapter, 0x06A4,0xffff); //maybe don't need to write here //disable update TSF rtw_write8(padapter, 0x0550, rtw_read8(padapter, 0x0550)|bit_4); pmlmeext->sitesurvey_res.channel_idx = 0; ptdls_sta->option = 5; _set_workitem(&ptdls_sta->option_workitem); break; case 5: survey_channel = pmlmeext->channel_set[pmlmeext->sitesurvey_res.channel_idx].ChannelNum; if(survey_channel){ SelectChannel(padapter, survey_channel); pmlmeinfo->tdls_cur_channel = survey_channel; pmlmeext->sitesurvey_res.channel_idx++; _set_timer(&ptdls_sta->option_timer, SURVEY_TO); }else{ SelectChannel(padapter, pmlmeext->cur_channel); //enable update TSF rtw_write8(padapter, 0x0550, rtw_read8(padapter, 0x0550)&(~bit_4)); rtw_write32(padapter, 0x0608, rtw_read32(padapter, 0x0608)|(bit_7)); if(pmlmeinfo->tdls_ch_sensing==1){ pmlmeinfo->tdls_ch_sensing=0; pmlmeinfo->tdls_cur_channel=1; min=pmlmeinfo->tdls_collect_pkt_num[0]; for(i=1; i<14-1; i++){ if(min > pmlmeinfo->tdls_collect_pkt_num[i]){ pmlmeinfo->tdls_cur_channel=i+1; min=pmlmeinfo->tdls_collect_pkt_num[i]; } pmlmeinfo->tdls_collect_pkt_num[i]=0; } pmlmeinfo->tdls_collect_pkt_num[0]=0; pmlmeinfo->tdls_candidate_ch=pmlmeinfo->tdls_cur_channel; DBG_8192C("TDLS channel sensing done, candidate channel: %02x\n", pmlmeinfo->tdls_candidate_ch); pmlmeinfo->tdls_cur_channel=0; } if(ptdls_sta->state & TDLS_PEER_SLEEP_STATE){ ptdls_sta->state |= TDLS_APSD_CHSW_STATE; }else{ //send null data with pwrbit==1 before send ch_switching_req to peer STA. issue_nulldata(padapter, 1); ptdls_sta->state |= TDLS_CH_SW_INITIATOR_STATE; issue_tdls_ch_switch_req(padapter, ptdls_sta->hwaddr); DBG_8192C("issue tdls ch switch req\n"); } } break; case 6: issue_nulldata(padapter, 1); SelectChannel(padapter, ptdls_sta->off_ch); DBG_8192C("change channel to tar ch:%02x\n", ptdls_sta->off_ch); ptdls_sta->state |= TDLS_AT_OFF_CH_STATE; ptdls_sta->state &= ~(TDLS_PEER_AT_OFF_STATE); _set_timer(&ptdls_sta->option_timer, (u32)ptdls_sta->ch_switch_time); break; case 7: _cancel_timer_ex(&ptdls_sta->base_ch_timer); _cancel_timer_ex(&ptdls_sta->off_ch_timer); SelectChannel(padapter, pmlmeext->cur_channel); ptdls_sta->state &= ~(TDLS_CH_SWITCH_ON_STATE | TDLS_PEER_AT_OFF_STATE | TDLS_AT_OFF_CH_STATE); DBG_8192C("go back to base channel\n "); issue_nulldata(padapter, 0); _set_timer(&ptdls_sta->option_timer, (u32)ptdls_sta->ch_switch_time); break; } }
void sd_int_dpc(PADAPTER padapter) { PHAL_DATA_TYPE phal; struct dvobj_priv *dvobj; struct intf_hdl * pintfhdl=&padapter->iopriv.intf; struct pwrctrl_priv *pwrctl; phal = GET_HAL_DATA(padapter); dvobj = adapter_to_dvobj(padapter); pwrctl = dvobj_to_pwrctl(dvobj); if (phal->sdio_hisr & SDIO_HISR_CPWM1) { struct reportpwrstate_parm report; #ifdef CONFIG_LPS_RPWM_TIMER u8 bcancelled; _cancel_timer(&(pwrctl->pwr_rpwm_timer), &bcancelled); #endif // CONFIG_LPS_RPWM_TIMER report.state = SdioLocalCmd52Read1Byte(padapter, SDIO_REG_HCPWM1_8723B); #ifdef CONFIG_LPS_LCLK //cpwm_int_hdl(padapter, &report); _set_workitem(&(pwrctl->cpwm_event)); #endif } if (phal->sdio_hisr & SDIO_HISR_TXERR) { u8 *status; u32 addr; status = rtw_malloc(4); if (status) { addr = REG_TXDMA_STATUS; HalSdioGetCmdAddr8723BSdio(padapter, WLAN_IOREG_DEVICE_ID, addr, &addr); _sd_read(pintfhdl, addr, 4, status); _sd_write(pintfhdl, addr, 4, status); DBG_8192C("%s: SDIO_HISR_TXERR (0x%08x)\n", __func__, le32_to_cpu(*(u32*)status)); rtw_mfree(status, 4); } else { DBG_8192C("%s: SDIO_HISR_TXERR, but can't allocate memory to read status!\n", __func__); } } if (phal->sdio_hisr & SDIO_HISR_TXBCNOK) { DBG_8192C("%s: SDIO_HISR_TXBCNOK\n", __func__); } if (phal->sdio_hisr & SDIO_HISR_TXBCNERR) { DBG_8192C("%s: SDIO_HISR_TXBCNERR\n", __func__); } #ifndef CONFIG_C2H_PACKET_EN if (phal->sdio_hisr & SDIO_HISR_C2HCMD) { struct c2h_evt_hdr_88xx *c2h_evt; DBG_8192C("%s: C2H Command\n", __func__); if ((c2h_evt = (struct c2h_evt_hdr_88xx*)rtw_zmalloc(16)) != NULL) { if (rtw_hal_c2h_evt_read(padapter, (u8 *)c2h_evt) == _SUCCESS) { if (c2h_id_filter_ccx_8723b((u8 *)c2h_evt)) { /* Handle CCX report here */ rtw_hal_c2h_handler(padapter, (u8 *)c2h_evt); rtw_mfree((u8*)c2h_evt, 16); } else { rtw_c2h_wk_cmd(padapter, (u8 *)c2h_evt); } } } else { /* Error handling for malloc fail */ if (rtw_cbuf_push(padapter->evtpriv.c2h_queue, (void*)NULL) != _SUCCESS) DBG_871X("%s rtw_cbuf_push fail\n", __func__); _set_workitem(&padapter->evtpriv.c2h_wk); } } #endif if (phal->sdio_hisr & SDIO_HISR_RXFOVW) { DBG_8192C("%s: Rx Overflow\n", __func__); } if (phal->sdio_hisr & SDIO_HISR_RXERR) { DBG_8192C("%s: Rx Error\n", __func__); } if (phal->sdio_hisr & SDIO_HISR_RX_REQUEST) { struct recv_buf *precvbuf; int alloc_fail_time=0; u32 hisr; // DBG_8192C("%s: RX Request, size=%d\n", __func__, phal->SdioRxFIFOSize); phal->sdio_hisr ^= SDIO_HISR_RX_REQUEST; do { phal->SdioRxFIFOSize = SdioLocalCmd52Read2Byte(padapter, SDIO_REG_RX0_REQ_LEN); if (phal->SdioRxFIFOSize != 0) { #ifdef CONFIG_MAC_LOOPBACK_DRIVER sd_recv_loopback(padapter, phal->SdioRxFIFOSize); #else precvbuf = sd_recv_rxfifo(padapter, phal->SdioRxFIFOSize); if (precvbuf) sd_rxhandler(padapter, precvbuf); else { alloc_fail_time++; DBG_871X("precvbuf is Null for %d times because alloc memory failed\n", alloc_fail_time); if (alloc_fail_time >= 10) break; } phal->SdioRxFIFOSize = 0; #endif } else break; hisr = 0; ReadInterrupt8723BSdio(padapter, &hisr); hisr &= SDIO_HISR_RX_REQUEST; if (!hisr) break; } while (1); if(alloc_fail_time==10) DBG_871X("exit because alloc memory failed more than 10 times \n"); } }
void sd_int_dpc(PADAPTER padapter) { HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); if (pHalData->sdio_hisr & SDIO_HISR_CPWM1) { struct reportpwrstate_parm report; _sdio_local_read(padapter, SDIO_REG_HCPWM1, 1, &report.state); #ifdef CONFIG_LPS_LCLK //88e's cpwm value only change BIT0, so driver need to add PS_STATE_S2 for LPS flow. //modify by Thomas. 2012/4/2. report.state |= PS_STATE_S2; //cpwm_int_hdl(padapter, &report); _set_workitem(&padapter->pwrctrlpriv.cpwm_event); #endif } if (pHalData->sdio_hisr & SDIO_HISR_TXERR) { u8 *status; u32 addr; status = _rtw_malloc(4); if (status) { addr = REG_TXDMA_STATUS; HalSdioGetCmdAddr8723ASdio(padapter, WLAN_IOREG_DEVICE_ID, addr, &addr); _sd_read(&padapter->dvobjpriv.intf_data, addr, 4, status); _sd_write(&padapter->dvobjpriv.intf_data, addr, 4, status); printk("%s: SDIO_HISR_TXERR (0x%08x)\n", __func__, le32_to_cpu(*(u32*)status)); _rtw_mfree(status, 4); } else { printk("%s: SDIO_HISR_TXERR, but can't allocate memory to read status!\n", __func__); } } if (pHalData->sdio_hisr & SDIO_HISR_TXBCNOK) { printk("%s: SDIO_HISR_TXBCNOK\n", __func__); } if (pHalData->sdio_hisr & SDIO_HISR_TXBCNERR) { printk("%s: SDIO_HISR_TXBCNERR\n", __func__); } if (pHalData->sdio_hisr & SDIO_HISR_C2HCMD) { printk("%s: C2H Command\n", __func__); } if (pHalData->sdio_hisr & SDIO_HISR_RX_REQUEST) { struct recv_buf *precvbuf; //printk("%s: RX Request, size=%d\n", __func__, phal->SdioRxFIFOSize); pHalData->sdio_hisr ^= SDIO_HISR_RX_REQUEST; #ifdef CONFIG_MAC_LOOPBACK_DRIVER sd_recv_loopback(padapter, pHalData->SdioRxFIFOSize); #else //Sometimes rx length will be zero. driver need to use cmd53 read again. if(pHalData->SdioRxFIFOSize == 0) { u8 data[4]; _sdio_local_read(padapter, SDIO_REG_RX0_REQ_LEN, 4, data); pHalData->SdioRxFIFOSize = le16_to_cpu(*(u16*)data); } if(pHalData->SdioRxFIFOSize) { precvbuf = sd_recv_rxfifo(padapter, pHalData->SdioRxFIFOSize); if (precvbuf) sd_rxhandler(padapter, precvbuf); pHalData->SdioRxFIFOSize = 0; } #endif } }