unsigned long acpi_fill_mcfg(unsigned long current)
{
device_t dev;
u32 pciexbar = 0;
u32 pciexbar_reg;
int max_buses;
int pci_dev_id;
for (pci_dev_id = PCI_DEVICE_ID_RG_MIN; pci_dev_id <= PCI_DEVICE_ID_RG_MAX; pci_dev_id++) {
dev = dev_find_device(PCI_VENDOR_ID_INTEL, pci_dev_id, 0);
if (dev)
break;
}
if (!dev)
return current;
pciexbar_reg = sideband_read(B_UNIT, BECREG);
/* MMCFG not supported or not enabled. */
if (!(pciexbar_reg & (1 << 0)))
return current;
/* 256MB ECAM range */
pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28));
max_buses = 256;
current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current,
pciexbar, 0x0, 0x0, max_buses - 1);
return current;
}
static u32 acpi_fill_mcfg(u32 current)
{
current += acpi_create_mcfg_mmconfig
((struct acpi_mcfg_mmconfig *)current,
CONFIG_PCIE_ECAM_BASE, 0x0, 0x0, 255);
return current;
}
unsigned long acpi_fill_mcfg(unsigned long current)
{
/* PCI Segment Group 0, Start Bus Number 0, End Bus Number is 255 */
current += acpi_create_mcfg_mmconfig((void *) current,
CONFIG_MMCONF_BASE_ADDRESS, 0, 0,
255);
return current;
}
unsigned long acpi_fill_mcfg(unsigned long current)
{
current += acpi_create_mcfg_mmconfig((struct acpi_mcfg_mmconfig *) current,
0xe0000000, 0x0, 0x0, 255);
return current;
}
unsigned long acpi_fill_mcfg(unsigned long current)
{
device_t dev;
struct resource *res;
dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_K8M890CE_5, 0);
if (!dev)
return current;
res = find_resource(dev, K8T890_MMCONFIG_MBAR);
if (res) {
current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)
current, res->base, 0x0, 0x0, 0xff);
}
return current;
}
unsigned long acpi_fill_mcfg(unsigned long current)
{
device_t dev;
u32 reg;
dev = dev_find_device(0x8086, 0x29c0, 0);
if (!dev)
return current;
reg = pci_read_config32(dev, 0x60);
if ((reg & 0x07) != 0x01) // require enabled + 256MB size
return current;
current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current,
reg & 0xf0000000, 0x0, 0x0, 255);
return current;
}
unsigned long acpi_fill_mcfg(unsigned long current)
{
device_t dev;
u32 pciexbar = 0;
u32 pciexbar_reg;
int max_buses;
dev = dev_find_device(0x8086, 0x27a0, 0);
if (!dev)
return current;
pciexbar_reg = pci_read_config32(dev, 0x48);
/* MMCFG not supported or not enabled. */
if (!(pciexbar_reg & (1 << 0)))
return current;
switch ((pciexbar_reg >> 1) & 3) {
case 0: /* 256MB */
pciexbar = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) |
(1 << 28));
max_buses = 256;
break;
case 1: /* 128M */
pciexbar = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) |
(1 << 28) | (1 << 27));
max_buses = 128;
break;
case 2: /* 64M */
pciexbar = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) |
(1 << 28) | (1 << 27) | (1 << 26));
max_buses = 64;
break;
default: /* RSVD */
return current;
}
if (!pciexbar)
return current;
#if CONFIG_GENERATE_ACPI_TABLES
current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current,
pciexbar, 0x0, 0x0, max_buses - 1);
#endif
return current;
}
unsigned long acpi_fill_mcfg(unsigned long current)
{
device_t dev;
u32 pciexbar = 0;
u32 pciexbar_reg;
int max_buses;
dev = dev_find_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_SB, 0);
if (!dev)
dev = dev_find_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_IB, 0);
if (!dev)
return current;
pciexbar_reg=pci_read_config32(dev, PCIEXBAR);
// MMCFG not supported or not enabled.
if (!(pciexbar_reg & (1 << 0)))
return current;
switch ((pciexbar_reg >> 1) & 3) {
case 0: // 256MB
pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28));
max_buses = 256;
break;
case 1: // 128M
pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27));
max_buses = 128;
break;
case 2: // 64M
pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)|(1 << 26));
max_buses = 64;
break;
default: // RSVD
return current;
}
if (!pciexbar)
return current;
current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current,
pciexbar, 0x0, 0x0, max_buses - 1);
return current;
}
unsigned long acpi_fill_mcfg(unsigned long current)
{
u32 pciexbar = 0;
u32 pciexbar_reg;
int max_buses;
pciexbar_reg = pci_read_config32(PCI_DEV(QUICKPATH_BUS, 0, 1), 0x50);
// MMCFG not supported or not enabled.
if (!(pciexbar_reg & (1 << 0)))
return current;
switch ((pciexbar_reg >> 1) & 3) {
case 0: // 256MB
pciexbar =
pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) |
(1 << 28));
max_buses = 256;
break;
case 1: // 128M
pciexbar =
pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) |
(1 << 28) | (1 << 27));
max_buses = 128;
break;
case 2: // 64M
pciexbar =
pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) |
(1 << 28) | (1 << 27) | (1 << 26));
max_buses = 64;
break;
default: // RSVD
return current;
}
if (!pciexbar)
return current;
current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current,
pciexbar, 0x0, 0x0, max_buses - 1);
return current;
}
unsigned long acpi_fill_mcfg(unsigned long current)
{
device_t dev;
u64 mmcfg;
dev = dev_find_device(0x1106, 0x324b, 0); // 0:0x13.0
if (!dev)
return current;
// MMCFG not supported or not enabled.
if ((pci_read_config8(dev, 0x40) & 0xC0) != 0xC0)
return current;
mmcfg = ((u64) pci_read_config8(dev, 0x41)) << 28;
if (!mmcfg)
return current;
current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current, mmcfg, 0x0, 0x0, 0xff);
return current;
}
unsigned long acpi_fill_mcfg(unsigned long current)
{
current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current,
MCFG_BASE_ADDRESS, 0, 0, 255);
return current;
}
