/***************************************************************************//**
* @brief main
*******************************************************************************/
int main(void)
{
Xil_ICacheEnable();
Xil_DCacheEnable();
gpio_init(GPIO_DEVICE_ID);
gpio_direction(54 + 46, 1);
spi_init(SPI_DEVICE_ID, 1, 0);
adc_init();
dac_init(DATA_SEL_DDS);
ad9361_phy = ad9361_init(&default_init_param);
ad9361_set_tx_fir_config(ad9361_phy, tx_fir_config);
ad9361_set_rx_fir_config(ad9361_phy, rx_fir_config);
#ifdef DAC_DMA
dac_init(DATA_SEL_DMA);
#else
dac_init(DATA_SEL_DDS);
#endif
#ifdef CAPTURE_SCRIPT
adc_capture(16384, ADC_DDR_BASEADDR);
while(1);
#endif
get_help(NULL, 0);
while(1)
{
console_get_command(received_cmd);
invalid_cmd = 0;
for(cmd = 0; cmd < cmd_no; cmd++)
{
param_no = 0;
cmd_type = console_check_commands(received_cmd, cmd_list[cmd].name,
param, ¶m_no);
if(cmd_type == UNKNOWN_CMD)
{
invalid_cmd++;
}
else
{
cmd_list[cmd].function(param, param_no);
}
}
if(invalid_cmd == cmd_no)
{
console_print("Invalid command!\n");
}
}
Xil_DCacheDisable();
Xil_ICacheDisable();
return 0;
}
/***************************************************************************//**
* @brief main
*******************************************************************************/
int initAd9361(void) {
int Status;
uint64_t Value;
uint8_t en_dis;
/*
* NOTE: The user has to choose the GPIO numbers according to desired
* carrier board. The following configuration is valid for boards other
* than the Fmcomms5.
*/
default_init_param.gpio_resetb = GPIO_RESET_PIN;
default_init_param.gpio_sync = -1;
default_init_param.gpio_cal_sw1 = -1;
default_init_param.gpio_cal_sw2 = -1;
/*
* Initialize the GPIO
*/
gpio_init(GPIO_DEVICE_ID);
gpio_direction(default_init_param.gpio_resetb, 1);
/*
* Initialize the SPI
*/
spi_init(SPI_DEVICE_ID, 1, 0);
/*
* Initialize AD9361
*/
Status = ad9361_init(&ad9361_phy, &default_init_param);
if (Status != 0) {
xil_printf("Could not initialize AD9361\r\n");
xil_printf("Status\t%d\r\n", Status);
return 1;
}
/*
* Sampling frequency
*/
Status = ad9361_set_tx_sampling_freq(ad9361_phy, SAMPLING_FREQ);
if (Status != 0) {
xil_printf("Could not set Tx sampling freq.\r\n");
return 1;
}
Status = ad9361_set_rx_sampling_freq(ad9361_phy, SAMPLING_FREQ);
if (Status != 0) {
xil_printf("Could not set Rx sampling freq.\r\n");
return 1;
}
/*
* Set Tx and Rx FIR
*/
Status = ad9361_set_tx_fir_config(ad9361_phy, tx_fir_config);
if (Status != 0) {
xil_printf("Could not set Tx FIR\r\n");
return 1;
}
Status = ad9361_set_rx_fir_config(ad9361_phy, rx_fir_config);
if (Status != 0) {
xil_printf("Could not set Rx FIR\r\n");
return 1;
}
// Enable both at the same time
Status = ad9361_set_trx_fir_en_dis(ad9361_phy, 1);
if (Status != 0) {
xil_printf("Could not enable Tx and Rx FIR\r\n");
return 1;
}
// Check status
Status = ad9361_get_tx_fir_en_dis(ad9361_phy, &en_dis);
if (Status == 0) {
xil_printf("Tx FIR status\t %d\r\n", en_dis);
} else {
xil_printf("Could not get Tx FIR enable\r\n");
return 1;
}
Status = ad9361_get_rx_fir_en_dis(ad9361_phy, &en_dis);
if (Status == 0) {
xil_printf("Rx FIR status\t %d\r\n", en_dis);
} else {
xil_printf("Could not get Rx FIR enable\r\n");
return 1;
}
/*
* Rf bandwidth
*/
Status = ad9361_set_tx_rf_bandwidth(ad9361_phy, RF_BW);
if (Status != 0) {
xil_printf("Could not set Tx Rf bandwidth\r\n");
return 1;
}
Status = ad9361_set_rx_rf_bandwidth(ad9361_phy, RF_BW);
if (Status != 0) {
xil_printf("Could not set Rx Rf bandwidth\r\n");
return 1;
}
/*
* Gain control mode
*/
Status = ad9361_set_rx_gain_control_mode(ad9361_phy, 0,
RF_GAIN_SLOWATTACK_AGC);
if (Status != 0) {
xil_printf("Could not set Rx gain control mode for channel 0\r\n");
return 1;
}
/*
* Hardware gains
*/
Status = ad9361_set_rx_rf_gain(ad9361_phy, 0, -10);
if (Status != 0) {
xil_printf("Could not set Rx gain for channel 0\r\n");
return 1;
}
Status = ad9361_get_rx_lo_freq(ad9361_phy, &Value);
if (Status == 0) {
xil_printf("LO Frequency\t %u \r\n", Value);
} else {
xil_printf("Could not get current LO frequency\r\n");
return 1;
}
#if ROE_CPRI_SINK == ROE_SINK_DAC
dac_init(ad9361_phy, DATA_SEL_DMA, 1);
#endif
#ifndef AXI_ADC_NOT_PRESENT
#if defined XILINX_PLATFORM && defined CAPTURE_SCRIPT
// NOTE: To prevent unwanted data loss, it's recommended to invalidate
// cache after each adc_capture() call, keeping in mind that the
// size of the capture and the start address must be alinged to the size
// of the cache line.
mdelay(1000);
adc_capture(16384, ADC_DDR_BASEADDR);
Xil_DCacheInvalidateRange(ADC_DDR_BASEADDR, 16384);
#endif
#endif
#ifdef CONSOLE_COMMANDS
get_help(NULL, 0);
while (1)
{
console_get_command(received_cmd);
invalid_cmd = 0;
for (cmd = 0; cmd < cmd_no; cmd++)
{
param_no = 0;
cmd_type = console_check_commands(received_cmd, cmd_list[cmd].name,
param, ¶m_no);
if (cmd_type == UNKNOWN_CMD)
{
invalid_cmd++;
}
else
{
cmd_list[cmd].function(param, param_no);
}
}
if (invalid_cmd == cmd_no)
{
console_print("Invalid command!\n");
}
}
#endif
printf("AD9361 Initialization Done.\n");
#ifdef XILINX_PLATFORM
Xil_DCacheDisable();
Xil_ICacheDisable();
#endif
return 0;
}
/***************************************************************************//**
* @brief main
*******************************************************************************/
int main(void)
{
#ifdef XILINX_PLATFORM
Xil_ICacheEnable();
Xil_DCacheEnable();
#endif
#ifdef ALTERA_PLATFORM
if (altera_bridge_init()) {
printf("Altera Bridge Init Error!\n");
return -1;
}
#endif
// NOTE: The user has to choose the GPIO numbers according to desired
// carrier board.
default_init_param.gpio_resetb = GPIO_RESET_PIN;
#ifdef FMCOMMS5
default_init_param.gpio_sync = GPIO_SYNC_PIN;
default_init_param.gpio_cal_sw1 = GPIO_CAL_SW1_PIN;
default_init_param.gpio_cal_sw2 = GPIO_CAL_SW2_PIN;
default_init_param.rx1rx2_phase_inversion_en = 1;
#else
default_init_param.gpio_sync = -1;
default_init_param.gpio_cal_sw1 = -1;
default_init_param.gpio_cal_sw2 = -1;
#endif
#ifdef LINUX_PLATFORM
gpio_init(default_init_param.gpio_resetb);
#else
gpio_init(GPIO_DEVICE_ID);
#endif
gpio_direction(default_init_param.gpio_resetb, 1);
spi_init(SPI_DEVICE_ID, 1, 0);
if (AD9364_DEVICE)
default_init_param.dev_sel = ID_AD9364;
if (AD9363A_DEVICE)
default_init_param.dev_sel = ID_AD9363A;
#if defined FMCOMMS5 || defined PICOZED_SDR || defined PICOZED_SDR_CMOS
default_init_param.xo_disable_use_ext_refclk_enable = 1;
#endif
#ifdef PICOZED_SDR_CMOS
default_init_param.swap_ports_enable = 1;
default_init_param.lvds_mode_enable = 0;
default_init_param.lvds_rx_onchip_termination_enable = 0;
default_init_param.full_port_enable = 1;
default_init_param.digital_interface_tune_fir_disable = 1;
#endif
ad9361_init(&ad9361_phy, &default_init_param);
ad9361_set_tx_fir_config(ad9361_phy, tx_fir_config);
ad9361_set_rx_fir_config(ad9361_phy, rx_fir_config);
#ifdef FMCOMMS5
#ifdef LINUX_PLATFORM
gpio_init(default_init_param.gpio_sync);
#endif
gpio_direction(default_init_param.gpio_sync, 1);
default_init_param.id_no = 1;
default_init_param.gpio_resetb = GPIO_RESET_PIN_2;
#ifdef LINUX_PLATFORM
gpio_init(default_init_param.gpio_resetb);
#endif
default_init_param.gpio_sync = -1;
default_init_param.gpio_cal_sw1 = -1;
default_init_param.gpio_cal_sw2 = -1;
default_init_param.rx_synthesizer_frequency_hz = 2300000000UL;
default_init_param.tx_synthesizer_frequency_hz = 2300000000UL;
gpio_direction(default_init_param.gpio_resetb, 1);
ad9361_init(&ad9361_phy_b, &default_init_param);
ad9361_set_tx_fir_config(ad9361_phy_b, tx_fir_config);
ad9361_set_rx_fir_config(ad9361_phy_b, rx_fir_config);
#endif
#ifndef AXI_ADC_NOT_PRESENT
#if defined XILINX_PLATFORM || defined LINUX_PLATFORM
#ifdef DAC_DMA
#ifdef FMCOMMS5
dac_init(ad9361_phy_b, DATA_SEL_DMA, 0);
#endif
dac_init(ad9361_phy, DATA_SEL_DMA, 1);
#else
#ifdef FMCOMMS5
dac_init(ad9361_phy_b, DATA_SEL_DDS, 0);
#endif
dac_init(ad9361_phy, DATA_SEL_DDS, 1);
#endif
#endif
#endif
#ifdef FMCOMMS5
ad9361_do_mcs(ad9361_phy, ad9361_phy_b);
#endif
#ifndef AXI_ADC_NOT_PRESENT
#if defined XILINX_PLATFORM && defined CAPTURE_SCRIPT
// NOTE: To prevent unwanted data loss, it's recommended to invalidate
// cache after each adc_capture() call, keeping in mind that the
// size of the capture and the start address must be alinged to the size
// of the cache line.
mdelay(1000);
adc_capture(16384, ADC_DDR_BASEADDR);
Xil_DCacheInvalidateRange(ADC_DDR_BASEADDR, 16384);
#endif
#endif
#ifdef CONSOLE_COMMANDS
get_help(NULL, 0);
while(1)
{
console_get_command(received_cmd);
invalid_cmd = 0;
for(cmd = 0; cmd < cmd_no; cmd++)
{
param_no = 0;
cmd_type = console_check_commands(received_cmd, cmd_list[cmd].name,
param, ¶m_no);
if(cmd_type == UNKNOWN_CMD)
{
invalid_cmd++;
}
else
{
cmd_list[cmd].function(param, param_no);
}
}
if(invalid_cmd == cmd_no)
{
console_print("Invalid command!\n");
}
}
#endif
printf("Done.\n");
#ifdef TDD_SWITCH_STATE_EXAMPLE
uint32_t ensm_mode;
if (!ad9361_phy->pdata->fdd) {
if (ad9361_phy->pdata->ensm_pin_ctrl) {
gpio_direction(GPIO_ENABLE_PIN, 1);
gpio_direction(GPIO_TXNRX_PIN, 1);
gpio_set_value(GPIO_ENABLE_PIN, 0);
gpio_set_value(GPIO_TXNRX_PIN, 0);
udelay(10);
ad9361_get_en_state_machine_mode(ad9361_phy, &ensm_mode);
printf("TXNRX control - Alert: %s\n",
ensm_mode == ENSM_MODE_ALERT ? "OK" : "Error");
mdelay(1000);
if (ad9361_phy->pdata->ensm_pin_pulse_mode) {
while(1) {
gpio_set_value(GPIO_TXNRX_PIN, 0);
udelay(10);
gpio_set_value(GPIO_ENABLE_PIN, 1);
udelay(10);
gpio_set_value(GPIO_ENABLE_PIN, 0);
ad9361_get_en_state_machine_mode(ad9361_phy, &ensm_mode);
printf("TXNRX Pulse control - RX: %s\n",
ensm_mode == ENSM_MODE_RX ? "OK" : "Error");
mdelay(1000);
gpio_set_value(GPIO_ENABLE_PIN, 1);
udelay(10);
gpio_set_value(GPIO_ENABLE_PIN, 0);
ad9361_get_en_state_machine_mode(ad9361_phy, &ensm_mode);
printf("TXNRX Pulse control - Alert: %s\n",
ensm_mode == ENSM_MODE_ALERT ? "OK" : "Error");
mdelay(1000);
gpio_set_value(GPIO_TXNRX_PIN, 1);
udelay(10);
gpio_set_value(GPIO_ENABLE_PIN, 1);
udelay(10);
gpio_set_value(GPIO_ENABLE_PIN, 0);
ad9361_get_en_state_machine_mode(ad9361_phy, &ensm_mode);
printf("TXNRX Pulse control - TX: %s\n",
ensm_mode == ENSM_MODE_TX ? "OK" : "Error");
mdelay(1000);
gpio_set_value(GPIO_ENABLE_PIN, 1);
udelay(10);
gpio_set_value(GPIO_ENABLE_PIN, 0);
ad9361_get_en_state_machine_mode(ad9361_phy, &ensm_mode);
printf("TXNRX Pulse control - Alert: %s\n",
ensm_mode == ENSM_MODE_ALERT ? "OK" : "Error");
mdelay(1000);
}
} else {
while(1) {
gpio_set_value(GPIO_TXNRX_PIN, 0);
udelay(10);
gpio_set_value(GPIO_ENABLE_PIN, 1);
udelay(10);
ad9361_get_en_state_machine_mode(ad9361_phy, &ensm_mode);
printf("TXNRX control - RX: %s\n",
ensm_mode == ENSM_MODE_RX ? "OK" : "Error");
mdelay(1000);
gpio_set_value(GPIO_ENABLE_PIN, 0);
udelay(10);
ad9361_get_en_state_machine_mode(ad9361_phy, &ensm_mode);
printf("TXNRX control - Alert: %s\n",
ensm_mode == ENSM_MODE_ALERT ? "OK" : "Error");
mdelay(1000);
gpio_set_value(GPIO_TXNRX_PIN, 1);
udelay(10);
gpio_set_value(GPIO_ENABLE_PIN, 1);
udelay(10);
ad9361_get_en_state_machine_mode(ad9361_phy, &ensm_mode);
printf("TXNRX control - TX: %s\n",
ensm_mode == ENSM_MODE_TX ? "OK" : "Error");
mdelay(1000);
gpio_set_value(GPIO_ENABLE_PIN, 0);
udelay(10);
ad9361_get_en_state_machine_mode(ad9361_phy, &ensm_mode);
printf("TXNRX control - Alert: %s\n",
ensm_mode == ENSM_MODE_ALERT ? "OK" : "Error");
mdelay(1000);
}
}
} else {
while(1) {
ad9361_set_en_state_machine_mode(ad9361_phy, ENSM_MODE_RX);
ad9361_get_en_state_machine_mode(ad9361_phy, &ensm_mode);
printf("SPI control - RX: %s\n",
ensm_mode == ENSM_MODE_RX ? "OK" : "Error");
mdelay(1000);
ad9361_set_en_state_machine_mode(ad9361_phy, ENSM_MODE_ALERT);
ad9361_get_en_state_machine_mode(ad9361_phy, &ensm_mode);
printf("SPI control - Alert: %s\n",
ensm_mode == ENSM_MODE_ALERT ? "OK" : "Error");
mdelay(1000);
ad9361_set_en_state_machine_mode(ad9361_phy, ENSM_MODE_TX);
ad9361_get_en_state_machine_mode(ad9361_phy, &ensm_mode);
printf("SPI control - TX: %s\n",
ensm_mode == ENSM_MODE_TX ? "OK" : "Error");
mdelay(1000);
ad9361_set_en_state_machine_mode(ad9361_phy, ENSM_MODE_ALERT);
ad9361_get_en_state_machine_mode(ad9361_phy, &ensm_mode);
printf("SPI control - Alert: %s\n",
ensm_mode == ENSM_MODE_ALERT ? "OK" : "Error");
mdelay(1000);
}
}
}
#endif
#ifdef XILINX_PLATFORM
Xil_DCacheDisable();
Xil_ICacheDisable();
#endif
#ifdef ALTERA_PLATFORM
if (altera_bridge_uninit()) {
printf("Altera Bridge Uninit Error!\n");
return -1;
}
#endif
return 0;
}
/***************************************************************************//**
* @brief main
*******************************************************************************/
int main(void)
{
#ifdef XILINX_PLATFORM
Xil_ICacheEnable();
Xil_DCacheEnable();
#endif
// NOTE: The user has to choose the GPIO numbers according to desired
// carrier board.
default_init_param.gpio_resetb = GPIO_RESET_PIN;
#ifdef FMCOMMS5
default_init_param.gpio_sync = GPIO_SYNC_PIN;
default_init_param.gpio_cal_sw1 = GPIO_CAL_SW1_PIN;
default_init_param.gpio_cal_sw2 = GPIO_CAL_SW2_PIN;
#else
default_init_param.gpio_sync = -1;
default_init_param.gpio_cal_sw1 = -1;
default_init_param.gpio_cal_sw2 = -1;
#endif
#ifdef LINUX_PLATFORM
gpio_init(default_init_param.gpio_resetb);
#else
gpio_init(GPIO_DEVICE_ID);
#endif
gpio_direction(default_init_param.gpio_resetb, 1);
spi_init(SPI_DEVICE_ID, 1, 0);
#if defined FMCOMMS5 || defined PICOZED_SDR
default_init_param.xo_disable_use_ext_refclk_enable = 1;
#endif
ad9361_init(&ad9361_phy, &default_init_param);
ad9361_set_tx_fir_config(ad9361_phy, tx_fir_config);
ad9361_set_rx_fir_config(ad9361_phy, rx_fir_config);
#ifdef FMCOMMS5
#ifdef LINUX_PLATFORM
gpio_init(default_init_param.gpio_sync);
#endif
gpio_direction(default_init_param.gpio_sync, 1);
default_init_param.id_no = 1;
default_init_param.gpio_resetb = GPIO_RESET_PIN_2;
#ifdef LINUX_PLATFORM
gpio_init(default_init_param.gpio_resetb);
#endif
default_init_param.gpio_sync = -1;
default_init_param.gpio_cal_sw1 = -1;
default_init_param.gpio_cal_sw2 = -1;
default_init_param.rx_synthesizer_frequency_hz = 2300000000UL;
default_init_param.tx_synthesizer_frequency_hz = 2300000000UL;
gpio_direction(default_init_param.gpio_resetb, 1);
ad9361_init(&ad9361_phy_b, &default_init_param);
ad9361_set_tx_fir_config(ad9361_phy_b, tx_fir_config);
ad9361_set_rx_fir_config(ad9361_phy_b, rx_fir_config);
#endif
#if defined XILINX_PLATFORM || defined LINUX_PLATFORM
#ifdef DAC_DMA
#ifdef FMCOMMS5
dac_init(ad9361_phy_b, DATA_SEL_DMA, 0);
#endif
dac_init(ad9361_phy, DATA_SEL_DMA, 1);
#else
#ifdef FMCOMMS5
dac_init(ad9361_phy_b, DATA_SEL_DDS, 0);
#endif
dac_init(ad9361_phy, DATA_SEL_DDS, 1);
#endif
#endif
#ifdef FMCOMMS5
ad9361_do_mcs(ad9361_phy, ad9361_phy_b);
#endif
#if defined XILINX_PLATFORM && defined CAPTURE_SCRIPT
// NOTE: To prevent unwanted data loss, it's recommended to invalidate
// cache after each adc_capture() call, keeping in mind that the
// size of the capture and the start address must be alinged to the size
// of the cache line.
mdelay(1000);
adc_capture(16384, ADC_DDR_BASEADDR);
Xil_DCacheInvalidateRange(ADC_DDR_BASEADDR, 16384);
#endif
#ifdef CONSOLE_COMMANDS
get_help(NULL, 0);
while(1)
{
console_get_command(received_cmd);
invalid_cmd = 0;
for(cmd = 0; cmd < cmd_no; cmd++)
{
param_no = 0;
cmd_type = console_check_commands(received_cmd, cmd_list[cmd].name,
param, ¶m_no);
if(cmd_type == UNKNOWN_CMD)
{
invalid_cmd++;
}
else
{
cmd_list[cmd].function(param, param_no);
}
}
if(invalid_cmd == cmd_no)
{
console_print("Invalid command!\n");
}
}
#endif
printf("Done.\n");
#ifdef XILINX_PLATFORM
Xil_DCacheDisable();
Xil_ICacheDisable();
#endif
return 0;
}
