/** * @brief Configures and activates the ADC peripheral. * * @param[in] adcp pointer to the @p ADCDriver object * * @notapi */ void adc_lld_start(ADCDriver *adcp) { /* Handling the default configuration.*/ if (adcp->config == NULL) { adcp->config = &default_config; } /* If in stopped state then enables the ADC and DMA clocks.*/ if (adcp->state == ADC_STOP) { #if STM32_ADC_USE_ADC1 if (&ADCD1 == adcp) { bool b; b = dmaStreamAllocate(adcp->dmastp, STM32_ADC_ADC12_DMA_IRQ_PRIORITY, (stm32_dmaisr_t)adc_lld_serve_dma_interrupt, (void *)adcp); osalDbgAssert(!b, "stream already allocated"); rccEnableADC12(FALSE); } #endif /* STM32_ADC_USE_ADC1 */ #if STM32_ADC_USE_ADC3 if (&ADCD3 == adcp) { bool b; b = dmaStreamAllocate(adcp->dmastp, STM32_ADC_ADC34_DMA_IRQ_PRIORITY, (stm32_dmaisr_t)adc_lld_serve_dma_interrupt, (void *)adcp); osalDbgAssert(!b, "stream already allocated"); rccEnableADC34(FALSE); } #endif /* STM32_ADC_USE_ADC2 */ /* Setting DMA peripheral-side pointer.*/ #if STM32_ADC_DUAL_MODE dmaStreamSetPeripheral(adcp->dmastp, &adcp->adcc->CDR); #else dmaStreamSetPeripheral(adcp->dmastp, &adcp->adcm->DR); #endif /* Clock source setting.*/ adcp->adcc->CCR = STM32_ADC_ADC12_CLOCK_MODE | ADC_DMA_MDMA; /* Differential channels setting.*/ #if STM32_ADC_DUAL_MODE adcp->adcm->DIFSEL = adcp->config->difsel; adcp->adcs->DIFSEL = adcp->config->difsel; #else adcp->adcm->DIFSEL = adcp->config->difsel; #endif /* Master ADC calibration.*/ adc_lld_vreg_on(adcp); adc_lld_calibrate(adcp); /* Master ADC enabled here in order to reduce conversions latencies.*/ adc_lld_analog_on(adcp); } }
/** * @brief Configures and activates the ADC peripheral. * * @param[in] adcp pointer to the @p ADCDriver object * * @notapi */ void adc_lld_start(ADCDriver *adcp) { /* Handling the default configuration.*/ if (adcp->config == NULL) { adcp->config = &default_config; } /* If in stopped state then enables the ADC and DMA clocks.*/ if (adcp->state == ADC_STOP) { #if STM32_ADC_USE_ADC1 if (&ADCD1 == adcp) { adcp->dmastp = dmaStreamAllocI(STM32_ADC_ADC1_DMA_STREAM, STM32_ADC_ADC1_DMA_IRQ_PRIORITY, (stm32_dmaisr_t)adc_lld_serve_dma_interrupt, (void *)adcp); osalDbgAssert(adcp->dmastp != NULL, "unable to allocate stream"); clkmask |= (1 << 0); #if defined(STM32F3XX) rccEnableADC12(true); #endif #if defined(STM32L4XX) || defined(STM32L4XXP) rccEnableADC123(true); #endif #if STM32_DMA_SUPPORTS_DMAMUX dmaSetRequestSource(adcp->dmastp, STM32_DMAMUX1_ADC1); #endif } #endif /* STM32_ADC_USE_ADC1 */ #if STM32_ADC_USE_ADC2 if (&ADCD2 == adcp) { adcp->dmastp = dmaStreamAllocI(STM32_ADC_ADC2_DMA_STREAM, STM32_ADC_ADC2_DMA_IRQ_PRIORITY, (stm32_dmaisr_t)adc_lld_serve_dma_interrupt, (void *)adcp); osalDbgAssert(adcp->dmastp != NULL, "unable to allocate stream"); clkmask |= (1 << 1); #if defined(STM32F3XX) rccEnableADC12(true); #endif #if defined(STM32L4XX) || defined(STM32L4XXP) rccEnableADC123(true); #endif #if STM32_DMA_SUPPORTS_DMAMUX dmaSetRequestSource(adcp->dmastp, STM32_DMAMUX1_ADC2); #endif } #endif /* STM32_ADC_USE_ADC2 */ #if STM32_ADC_USE_ADC3 if (&ADCD3 == adcp) { adcp->dmastp = dmaStreamAllocI(STM32_ADC_ADC3_DMA_STREAM, STM32_ADC_ADC3_DMA_IRQ_PRIORITY, (stm32_dmaisr_t)adc_lld_serve_dma_interrupt, (void *)adcp); osalDbgAssert(adcp->dmastp != NULL, "unable to allocate stream"); clkmask |= (1 << 2); #if defined(STM32F3XX) rccEnableADC34(true); #endif #if defined(STM32L4XX) || defined(STM32L4XXP) rccEnableADC123(true); #endif #if STM32_DMA_SUPPORTS_DMAMUX dmaSetRequestSource(adcp->dmastp, STM32_DMAMUX1_ADC3); #endif } #endif /* STM32_ADC_USE_ADC3 */ #if STM32_ADC_USE_ADC4 if (&ADCD4 == adcp) { adcp->dmastp = dmaStreamAllocI(STM32_ADC_ADC4_DMA_STREAM, STM32_ADC_ADC4_DMA_IRQ_PRIORITY, (stm32_dmaisr_t)adc_lld_serve_dma_interrupt, (void *)adcp); osalDbgAssert(adcp->dmastp != NULL, "unable to allocate stream"); clkmask |= (1 << 3); #if defined(STM32F3XX) rccEnableADC34(true); #endif #if defined(STM32L4XX) || defined(STM32L4XXP) rccEnableADC123(true); #endif #if STM32_DMA_SUPPORTS_DMAMUX dmaSetRequestSource(adcp->dmastp, STM32_DMAMUX1_ADC4); #endif } #endif /* STM32_ADC_USE_ADC4 */ /* Setting DMA peripheral-side pointer.*/ #if STM32_ADC_DUAL_MODE dmaStreamSetPeripheral(adcp->dmastp, &adcp->adcc->CDR); #else dmaStreamSetPeripheral(adcp->dmastp, &adcp->adcm->DR); #endif /* Differential channels setting.*/ #if STM32_ADC_DUAL_MODE adcp->adcm->DIFSEL = adcp->config->difsel; adcp->adcs->DIFSEL = adcp->config->difsel; #else adcp->adcm->DIFSEL = adcp->config->difsel; #endif /* Master ADC calibration.*/ adc_lld_vreg_on(adcp); adc_lld_calibrate(adcp); /* Master ADC enabled here in order to reduce conversions latencies.*/ adc_lld_analog_on(adcp); } }