static void cortexa_mem_read(target *t, void *dest, target_addr src, size_t len) { /* Clean cache before reading */ for (uint32_t cl = src & ~(CACHE_LINE_LENGTH-1); cl < src + len; cl += CACHE_LINE_LENGTH) { write_gpreg(t, 0, cl); apb_write(t, DBGITR, MCR | DCCMVAC); } ADIv5_AP_t *ahb = ((struct cortexa_priv*)t->priv)->ahb; adiv5_mem_read(ahb, dest, va_to_pa(t, src), len); }
static uint32_t adiv5_mem_read32(ADIv5_AP_t *ap, uint32_t addr) { uint32_t ret; adiv5_mem_read(ap, &ret, addr, sizeof(ret)); return ret; }