static void a2xx_drawctxt_draw_workaround(struct adreno_device *adreno_dev, struct adreno_context *context) { struct kgsl_device *device = &adreno_dev->dev; unsigned int cmd[11]; unsigned int *cmds = &cmd[0]; if (adreno_is_a225(adreno_dev)) { adreno_dev->gpudev->ctx_switches_since_last_draw++; if (adreno_dev->gpudev->ctx_switches_since_last_draw > ADRENO_NUM_CTX_SWITCH_ALLOWED_BEFORE_DRAW) adreno_dev->gpudev->ctx_switches_since_last_draw = 0; else return; *cmds++ = cp_type3_packet(CP_SET_CONSTANT, 2); *cmds++ = (0x4 << 16) | (REG_PA_SU_SC_MODE_CNTL - 0x2000); *cmds++ = 0; *cmds++ = cp_type3_packet(CP_DRAW_INDX, 5); *cmds++ = 0; *cmds++ = 1<<14; *cmds++ = 0; *cmds++ = device->mmu.setstate_memory.gpuaddr; *cmds++ = 0; *cmds++ = cp_type3_packet(CP_WAIT_FOR_IDLE, 1); *cmds++ = 0x00000000; } else { *cmds++ = cp_type3_packet(CP_SET_SHADER_BASES, 1); *cmds++ = adreno_encode_istore_size(adreno_dev) | adreno_dev->pix_shader_start; } adreno_ringbuffer_issuecmds(device, context, KGSL_CMD_FLAGS_PMODE, &cmd[0], cmds - cmd); }
int adreno_ringbuffer_start(struct adreno_ringbuffer *rb, unsigned int init_ram) { int status; /*cp_rb_cntl_u cp_rb_cntl; */ union reg_cp_rb_cntl cp_rb_cntl; unsigned int *cmds, rb_cntl; struct kgsl_device *device = rb->device; struct adreno_device *adreno_dev = ADRENO_DEVICE(device); uint cmds_gpu; if (rb->flags & KGSL_FLAGS_STARTED) return 0; if (init_ram) { rb->timestamp = 0; GSL_RB_INIT_TIMESTAMP(rb); } kgsl_sharedmem_set(&rb->memptrs_desc, 0, 0, sizeof(struct kgsl_rbmemptrs)); kgsl_sharedmem_set(&rb->buffer_desc, 0, 0xAA, (rb->sizedwords << 2)); adreno_regwrite(device, REG_CP_RB_WPTR_BASE, (rb->memptrs_desc.gpuaddr + GSL_RB_MEMPTRS_WPTRPOLL_OFFSET)); /* setup WPTR delay */ adreno_regwrite(device, REG_CP_RB_WPTR_DELAY, 0 /*0x70000010 */); /*setup REG_CP_RB_CNTL */ adreno_regread(device, REG_CP_RB_CNTL, &rb_cntl); cp_rb_cntl.val = rb_cntl; /* * The size of the ringbuffer in the hardware is the log2 * representation of the size in quadwords (sizedwords / 2) */ cp_rb_cntl.f.rb_bufsz = ilog2(rb->sizedwords >> 1); /* * Specify the quadwords to read before updating mem RPTR. * Like above, pass the log2 representation of the blocksize * in quadwords. */ cp_rb_cntl.f.rb_blksz = ilog2(KGSL_RB_BLKSIZE >> 3); cp_rb_cntl.f.rb_poll_en = GSL_RB_CNTL_POLL_EN; /* WPTR polling */ /* mem RPTR writebacks */ cp_rb_cntl.f.rb_no_update = GSL_RB_CNTL_NO_UPDATE; adreno_regwrite(device, REG_CP_RB_CNTL, cp_rb_cntl.val); adreno_regwrite(device, REG_CP_RB_BASE, rb->buffer_desc.gpuaddr); adreno_regwrite(device, REG_CP_RB_RPTR_ADDR, rb->memptrs_desc.gpuaddr + GSL_RB_MEMPTRS_RPTR_OFFSET); /* explicitly clear all cp interrupts */ adreno_regwrite(device, REG_CP_INT_ACK, 0xFFFFFFFF); /* setup scratch/timestamp */ adreno_regwrite(device, REG_SCRATCH_ADDR, device->memstore.gpuaddr + KGSL_DEVICE_MEMSTORE_OFFSET(soptimestamp)); adreno_regwrite(device, REG_SCRATCH_UMSK, GSL_RB_MEMPTRS_SCRATCH_MASK); /* update the eoptimestamp field with the last retired timestamp */ kgsl_sharedmem_writel(&device->memstore, KGSL_DEVICE_MEMSTORE_OFFSET(eoptimestamp), rb->timestamp); /* load the CP ucode */ status = adreno_ringbuffer_load_pm4_ucode(device); if (status != 0) return status; /* load the prefetch parser ucode */ status = adreno_ringbuffer_load_pfp_ucode(device); if (status != 0) return status; adreno_regwrite(device, REG_CP_QUEUE_THRESHOLDS, 0x000C0804); rb->rptr = 0; rb->wptr = 0; /* clear ME_HALT to start micro engine */ adreno_regwrite(device, REG_CP_ME_CNTL, 0); /* ME_INIT */ cmds = adreno_ringbuffer_allocspace(rb, 19); cmds_gpu = rb->buffer_desc.gpuaddr + sizeof(uint)*(rb->wptr-19); GSL_RB_WRITE(cmds, cmds_gpu, CP_HDR_ME_INIT); /* All fields present (bits 9:0) */ GSL_RB_WRITE(cmds, cmds_gpu, 0x000003ff); /* Disable/Enable Real-Time Stream processing (present but ignored) */ GSL_RB_WRITE(cmds, cmds_gpu, 0x00000000); /* Enable (2D <-> 3D) implicit synchronization (present but ignored) */ GSL_RB_WRITE(cmds, cmds_gpu, 0x00000000); GSL_RB_WRITE(cmds, cmds_gpu, SUBBLOCK_OFFSET(REG_RB_SURFACE_INFO)); GSL_RB_WRITE(cmds, cmds_gpu, SUBBLOCK_OFFSET(REG_PA_SC_WINDOW_OFFSET)); GSL_RB_WRITE(cmds, cmds_gpu, SUBBLOCK_OFFSET(REG_VGT_MAX_VTX_INDX)); GSL_RB_WRITE(cmds, cmds_gpu, SUBBLOCK_OFFSET(REG_SQ_PROGRAM_CNTL)); GSL_RB_WRITE(cmds, cmds_gpu, SUBBLOCK_OFFSET(REG_RB_DEPTHCONTROL)); GSL_RB_WRITE(cmds, cmds_gpu, SUBBLOCK_OFFSET(REG_PA_SU_POINT_SIZE)); GSL_RB_WRITE(cmds, cmds_gpu, SUBBLOCK_OFFSET(REG_PA_SC_LINE_CNTL)); GSL_RB_WRITE(cmds, cmds_gpu, SUBBLOCK_OFFSET(REG_PA_SU_POLY_OFFSET_FRONT_SCALE)); /* Instruction memory size: */ GSL_RB_WRITE(cmds, cmds_gpu, (adreno_encode_istore_size(adreno_dev) | adreno_dev->pix_shader_start)); /* Maximum Contexts */ GSL_RB_WRITE(cmds, cmds_gpu, 0x00000001); /* Write Confirm Interval and The CP will wait the * wait_interval * 16 clocks between polling */ GSL_RB_WRITE(cmds, cmds_gpu, 0x00000000); /* NQ and External Memory Swap */ GSL_RB_WRITE(cmds, cmds_gpu, 0x00000000); /* Protected mode error checking */ GSL_RB_WRITE(cmds, cmds_gpu, GSL_RB_PROTECTED_MODE_CONTROL); /* Disable header dumping and Header dump address */ GSL_RB_WRITE(cmds, cmds_gpu, 0x00000000); /* Header dump size */ GSL_RB_WRITE(cmds, cmds_gpu, 0x00000000); adreno_ringbuffer_submit(rb); /* idle device to validate ME INIT */ status = adreno_idle(device); if (status == 0) rb->flags |= KGSL_FLAGS_STARTED; return status; }
/*copy colour, depth, & stencil buffers from system memory to graphics memory*/ static unsigned int *build_sys2gmem_cmds(struct adreno_device *adreno_dev, struct adreno_context *drawctxt, struct gmem_shadow_t *shadow) { unsigned int *cmds = shadow->gmem_restore_commands; unsigned int *start = cmds; /* Store TP0_CHICKEN register */ *cmds++ = cp_type3_packet(CP_REG_TO_MEM, 2); *cmds++ = REG_TP0_CHICKEN; *cmds++ = tmp_ctx.chicken_restore; *cmds++ = cp_type3_packet(CP_WAIT_FOR_IDLE, 1); *cmds++ = 0; /* Set TP0_CHICKEN to zero */ *cmds++ = cp_type0_packet(REG_TP0_CHICKEN, 1); *cmds++ = 0x00000000; /* Set PA_SC_AA_CONFIG to 0 */ *cmds++ = cp_type0_packet(REG_PA_SC_AA_CONFIG, 1); *cmds++ = 0x00000000; /* shader constants */ /* vertex buffer constants */ *cmds++ = cp_type3_packet(CP_SET_CONSTANT, 7); *cmds++ = (0x1 << 16) | (9 * 6); /* valid(?) vtx constant flag & addr */ *cmds++ = shadow->quad_vertices.gpuaddr | 0x3; /* limit = 12 dwords */ *cmds++ = 0x00000030; /* valid(?) vtx constant flag & addr */ *cmds++ = shadow->quad_texcoords.gpuaddr | 0x3; /* limit = 8 dwords */ *cmds++ = 0x00000020; *cmds++ = 0; *cmds++ = 0; /* Invalidate L2 cache to make sure vertices are updated */ *cmds++ = cp_type0_packet(REG_TC_CNTL_STATUS, 1); *cmds++ = 0x1; cmds = program_shader(cmds, 0, sys2gmem_vtx_pgm, SYS2GMEM_VTX_PGM_LEN); /* Repartition shaders */ *cmds++ = cp_type0_packet(REG_SQ_INST_STORE_MANAGMENT, 1); *cmds++ = 0x180; /* Invalidate Vertex & Pixel instruction code address and sizes */ *cmds++ = cp_type3_packet(CP_INVALIDATE_STATE, 1); *cmds++ = 0x00000300; /* 0x100 = Vertex, 0x200 = Pixel */ *cmds++ = cp_type3_packet(CP_SET_SHADER_BASES, 1); *cmds++ = adreno_encode_istore_size(adreno_dev) | adreno_dev->pix_shader_start; /* Load the patched fragment shader stream */ cmds = program_shader(cmds, 1, sys2gmem_frag_pgm, SYS2GMEM_FRAG_PGM_LEN); /* SQ_PROGRAM_CNTL / SQ_CONTEXT_MISC */ *cmds++ = cp_type3_packet(CP_SET_CONSTANT, 3); *cmds++ = CP_REG(REG_SQ_PROGRAM_CNTL); *cmds++ = 0x10030002; *cmds++ = 0x00000008; *cmds++ = cp_type3_packet(CP_SET_CONSTANT, 2); *cmds++ = CP_REG(REG_PA_SC_AA_MASK); *cmds++ = 0x0000ffff; /* REG_PA_SC_AA_MASK */ if (!adreno_is_a22x(adreno_dev)) { /* PA_SC_VIZ_QUERY */ *cmds++ = cp_type3_packet(CP_SET_CONSTANT, 2); *cmds++ = CP_REG(REG_PA_SC_VIZ_QUERY); *cmds++ = 0x0; /*REG_PA_SC_VIZ_QUERY */ } /* RB_COLORCONTROL */ *cmds++ = cp_type3_packet(CP_SET_CONSTANT, 2); *cmds++ = CP_REG(REG_RB_COLORCONTROL); *cmds++ = 0x00000c20; *cmds++ = cp_type3_packet(CP_SET_CONSTANT, 4); *cmds++ = CP_REG(REG_VGT_MAX_VTX_INDX); *cmds++ = 0x00ffffff; /* mmVGT_MAX_VTX_INDX */ *cmds++ = 0x0; /* mmVGT_MIN_VTX_INDX */ *cmds++ = 0x00000000; /* mmVGT_INDX_OFFSET */ *cmds++ = cp_type3_packet(CP_SET_CONSTANT, 3); *cmds++ = CP_REG(REG_VGT_VERTEX_REUSE_BLOCK_CNTL); *cmds++ = 0x00000002; /* mmVGT_VERTEX_REUSE_BLOCK_CNTL */ *cmds++ = 0x00000002; /* mmVGT_OUT_DEALLOC_CNTL */ *cmds++ = cp_type3_packet(CP_SET_CONSTANT, 2); *cmds++ = CP_REG(REG_SQ_INTERPOLATOR_CNTL); *cmds++ = 0xffffffff; /* mmSQ_INTERPOLATOR_CNTL */ *cmds++ = cp_type3_packet(CP_SET_CONSTANT, 2); *cmds++ = CP_REG(REG_PA_SC_AA_CONFIG); *cmds++ = 0x00000000; /* REG_PA_SC_AA_CONFIG */ /* set REG_PA_SU_SC_MODE_CNTL * Front_ptype = draw triangles * Back_ptype = draw triangles * Provoking vertex = last */ *cmds++ = cp_type3_packet(CP_SET_CONSTANT, 2); *cmds++ = CP_REG(REG_PA_SU_SC_MODE_CNTL); *cmds++ = 0x00080240; /* texture constants */ *cmds++ = cp_type3_packet(CP_SET_CONSTANT, (SYS2GMEM_TEX_CONST_LEN + 1)); *cmds++ = (0x1 << 16) | (0 * 6); memcpy(cmds, sys2gmem_tex_const, SYS2GMEM_TEX_CONST_LEN << 2); cmds[0] |= (shadow->pitch >> 5) << 22; cmds[1] |= shadow->gmemshadow.gpuaddr | surface_format_table[shadow->format]; cmds[2] |= (shadow->width - 1) | (shadow->height - 1) << 13; cmds += SYS2GMEM_TEX_CONST_LEN; /* program surface info */ *cmds++ = cp_type3_packet(CP_SET_CONSTANT, 3); *cmds++ = CP_REG(REG_RB_SURFACE_INFO); *cmds++ = shadow->gmem_pitch; /* pitch, MSAA = 1 */ /* RB_COLOR_INFO Endian=none, Linear, Format=RGBA8888, Swap=0, * Base=gmem_base */ *cmds++ = (shadow-> format << RB_COLOR_INFO__COLOR_FORMAT__SHIFT) | tmp_ctx.gmem_base; /* RB_DEPTHCONTROL */ *cmds++ = cp_type3_packet(CP_SET_CONSTANT, 2); *cmds++ = CP_REG(REG_RB_DEPTHCONTROL); if (adreno_is_a22x(adreno_dev)) *cmds++ = 8; /* disable Z */ else *cmds++ = 0; /* disable Z */ /* Use maximum scissor values -- quad vertices already * have the correct bounds */ *cmds++ = cp_type3_packet(CP_SET_CONSTANT, 3); *cmds++ = CP_REG(REG_PA_SC_SCREEN_SCISSOR_TL); *cmds++ = (0 << 16) | 0; *cmds++ = ((0x1fff) << 16) | 0x1fff; *cmds++ = cp_type3_packet(CP_SET_CONSTANT, 3); *cmds++ = CP_REG(REG_PA_SC_WINDOW_SCISSOR_TL); *cmds++ = (unsigned int)((1U << 31) | (0 << 16) | 0); *cmds++ = ((0x1fff) << 16) | 0x1fff; *cmds++ = cp_type3_packet(CP_SET_CONSTANT, 2); *cmds++ = CP_REG(REG_PA_CL_VTE_CNTL); /* disable X/Y/Z transforms, X/Y/Z are premultiplied by W */ *cmds++ = 0x00000b00; /*load the viewport so that z scale = clear depth and z offset = 0.0f */ *cmds++ = cp_type3_packet(CP_SET_CONSTANT, 3); *cmds++ = CP_REG(REG_PA_CL_VPORT_ZSCALE); *cmds++ = 0xbf800000; *cmds++ = 0x0; *cmds++ = cp_type3_packet(CP_SET_CONSTANT, 2); *cmds++ = CP_REG(REG_RB_COLOR_MASK); *cmds++ = 0x0000000f; /* R = G = B = 1:enabled */ *cmds++ = cp_type3_packet(CP_SET_CONSTANT, 2); *cmds++ = CP_REG(REG_RB_COLOR_DEST_MASK); *cmds++ = 0xffffffff; *cmds++ = cp_type3_packet(CP_SET_CONSTANT, 3); *cmds++ = CP_REG(REG_SQ_WRAPPING_0); *cmds++ = 0x00000000; *cmds++ = 0x00000000; /* load the stencil ref value * $AAM - do this later */ *cmds++ = cp_type3_packet(CP_SET_CONSTANT, 2); *cmds++ = CP_REG(REG_RB_MODECONTROL); /* draw pixels with color and depth/stencil component */ *cmds++ = 0x4; *cmds++ = cp_type3_packet(CP_SET_CONSTANT, 2); *cmds++ = CP_REG(REG_PA_CL_CLIP_CNTL); *cmds++ = 0x00010000; if (adreno_is_a22x(adreno_dev)) { *cmds++ = cp_type3_packet(CP_SET_DRAW_INIT_FLAGS, 1); *cmds++ = 0; *cmds++ = cp_type3_packet(CP_SET_CONSTANT, 2); *cmds++ = CP_REG(REG_A220_RB_LRZ_VSC_CONTROL); *cmds++ = 0x0000000; *cmds++ = cp_type3_packet(CP_DRAW_INDX, 3); *cmds++ = 0; /* viz query info. */ /* PrimType=RectList, SrcSel=AutoIndex, VisCullMode=Ignore*/ *cmds++ = 0x00004088; *cmds++ = 3; /* NumIndices=3 */ } else { /* queue the draw packet */ *cmds++ = cp_type3_packet(CP_DRAW_INDX, 2); *cmds++ = 0; /* viz query info. */ /* PrimType=RectList, NumIndices=3, SrcSel=AutoIndex */ *cmds++ = 0x00030088; } /* create indirect buffer command for above command sequence */ create_ib1(drawctxt, shadow->gmem_restore, start, cmds); return cmds; }
/*copy colour, depth, & stencil buffers from graphics memory to system memory*/ static unsigned int *build_gmem2sys_cmds(struct adreno_device *adreno_dev, struct adreno_context *drawctxt, struct gmem_shadow_t *shadow) { unsigned int *cmds = shadow->gmem_save_commands; unsigned int *start = cmds; /* Calculate the new offset based on the adjusted base */ unsigned int bytesperpixel = format2bytesperpixel[shadow->format]; unsigned int addr = shadow->gmemshadow.gpuaddr; unsigned int offset = (addr - (addr & 0xfffff000)) / bytesperpixel; /* Store TP0_CHICKEN register */ *cmds++ = cp_type3_packet(CP_REG_TO_MEM, 2); *cmds++ = REG_TP0_CHICKEN; *cmds++ = tmp_ctx.chicken_restore; *cmds++ = cp_type3_packet(CP_WAIT_FOR_IDLE, 1); *cmds++ = 0; /* Set TP0_CHICKEN to zero */ *cmds++ = cp_type0_packet(REG_TP0_CHICKEN, 1); *cmds++ = 0x00000000; /* Set PA_SC_AA_CONFIG to 0 */ *cmds++ = cp_type0_packet(REG_PA_SC_AA_CONFIG, 1); *cmds++ = 0x00000000; /* program shader */ /* load shader vtx constants ... 5 dwords */ *cmds++ = cp_type3_packet(CP_SET_CONSTANT, 4); *cmds++ = (0x1 << 16) | SHADER_CONST_ADDR; *cmds++ = 0; /* valid(?) vtx constant flag & addr */ *cmds++ = shadow->quad_vertices.gpuaddr | 0x3; /* limit = 12 dwords */ *cmds++ = 0x00000030; /* Invalidate L2 cache to make sure vertices are updated */ *cmds++ = cp_type0_packet(REG_TC_CNTL_STATUS, 1); *cmds++ = 0x1; *cmds++ = cp_type3_packet(CP_SET_CONSTANT, 4); *cmds++ = CP_REG(REG_VGT_MAX_VTX_INDX); *cmds++ = 0x00ffffff; /* REG_VGT_MAX_VTX_INDX */ *cmds++ = 0x0; /* REG_VGT_MIN_VTX_INDX */ *cmds++ = 0x00000000; /* REG_VGT_INDX_OFFSET */ *cmds++ = cp_type3_packet(CP_SET_CONSTANT, 2); *cmds++ = CP_REG(REG_PA_SC_AA_MASK); *cmds++ = 0x0000ffff; /* REG_PA_SC_AA_MASK */ *cmds++ = cp_type3_packet(CP_SET_CONSTANT, 2); *cmds++ = CP_REG(REG_RB_COLORCONTROL); *cmds++ = 0x00000c20; /* Repartition shaders */ *cmds++ = cp_type0_packet(REG_SQ_INST_STORE_MANAGMENT, 1); *cmds++ = 0x180; /* Invalidate Vertex & Pixel instruction code address and sizes */ *cmds++ = cp_type3_packet(CP_INVALIDATE_STATE, 1); *cmds++ = 0x00003F00; *cmds++ = cp_type3_packet(CP_SET_SHADER_BASES, 1); *cmds++ = adreno_encode_istore_size(adreno_dev) | adreno_dev->pix_shader_start; /* load the patched vertex shader stream */ cmds = program_shader(cmds, 0, gmem2sys_vtx_pgm, GMEM2SYS_VTX_PGM_LEN); /* Load the patched fragment shader stream */ cmds = program_shader(cmds, 1, gmem2sys_frag_pgm, GMEM2SYS_FRAG_PGM_LEN); /* SQ_PROGRAM_CNTL / SQ_CONTEXT_MISC */ *cmds++ = cp_type3_packet(CP_SET_CONSTANT, 3); *cmds++ = CP_REG(REG_SQ_PROGRAM_CNTL); if (adreno_is_a22x(adreno_dev)) *cmds++ = 0x10018001; else *cmds++ = 0x10010001; *cmds++ = 0x00000008; /* resolve */ /* PA_CL_VTE_CNTL */ *cmds++ = cp_type3_packet(CP_SET_CONSTANT, 2); *cmds++ = CP_REG(REG_PA_CL_VTE_CNTL); /* disable X/Y/Z transforms, X/Y/Z are premultiplied by W */ *cmds++ = 0x00000b00; /* program surface info */ *cmds++ = cp_type3_packet(CP_SET_CONSTANT, 3); *cmds++ = CP_REG(REG_RB_SURFACE_INFO); *cmds++ = shadow->gmem_pitch; /* pitch, MSAA = 1 */ /* RB_COLOR_INFO Endian=none, Linear, Format=RGBA8888, Swap=0, * Base=gmem_base */ /* gmem base assumed 4K aligned. */ BUG_ON(tmp_ctx.gmem_base & 0xFFF); *cmds++ = (shadow-> format << RB_COLOR_INFO__COLOR_FORMAT__SHIFT) | tmp_ctx.gmem_base; /* disable Z */ *cmds++ = cp_type3_packet(CP_SET_CONSTANT, 2); *cmds++ = CP_REG(REG_RB_DEPTHCONTROL); if (adreno_is_a22x(adreno_dev)) *cmds++ = 0x08; else *cmds++ = 0; /* set REG_PA_SU_SC_MODE_CNTL * Front_ptype = draw triangles * Back_ptype = draw triangles * Provoking vertex = last */ *cmds++ = cp_type3_packet(CP_SET_CONSTANT, 2); *cmds++ = CP_REG(REG_PA_SU_SC_MODE_CNTL); *cmds++ = 0x00080240; /* Use maximum scissor values -- quad vertices already have the * correct bounds */ *cmds++ = cp_type3_packet(CP_SET_CONSTANT, 3); *cmds++ = CP_REG(REG_PA_SC_SCREEN_SCISSOR_TL); *cmds++ = (0 << 16) | 0; *cmds++ = (0x1fff << 16) | (0x1fff); *cmds++ = cp_type3_packet(CP_SET_CONSTANT, 3); *cmds++ = CP_REG(REG_PA_SC_WINDOW_SCISSOR_TL); *cmds++ = (unsigned int)((1U << 31) | (0 << 16) | 0); *cmds++ = (0x1fff << 16) | (0x1fff); /* load the viewport so that z scale = clear depth and * z offset = 0.0f */ *cmds++ = cp_type3_packet(CP_SET_CONSTANT, 3); *cmds++ = CP_REG(REG_PA_CL_VPORT_ZSCALE); *cmds++ = 0xbf800000; /* -1.0f */ *cmds++ = 0x0; *cmds++ = cp_type3_packet(CP_SET_CONSTANT, 2); *cmds++ = CP_REG(REG_RB_COLOR_MASK); *cmds++ = 0x0000000f; /* R = G = B = 1:enabled */ *cmds++ = cp_type3_packet(CP_SET_CONSTANT, 2); *cmds++ = CP_REG(REG_RB_COLOR_DEST_MASK); *cmds++ = 0xffffffff; *cmds++ = cp_type3_packet(CP_SET_CONSTANT, 3); *cmds++ = CP_REG(REG_SQ_WRAPPING_0); *cmds++ = 0x00000000; *cmds++ = 0x00000000; /* load the stencil ref value * $AAM - do this later */ /* load the COPY state */ *cmds++ = cp_type3_packet(CP_SET_CONSTANT, 6); *cmds++ = CP_REG(REG_RB_COPY_CONTROL); *cmds++ = 0; /* RB_COPY_CONTROL */ *cmds++ = addr & 0xfffff000; /* RB_COPY_DEST_BASE */ *cmds++ = shadow->pitch >> 5; /* RB_COPY_DEST_PITCH */ /* Endian=none, Linear, Format=RGBA8888,Swap=0,!Dither, * MaskWrite:R=G=B=A=1 */ *cmds++ = 0x0003c008 | (shadow->format << RB_COPY_DEST_INFO__COPY_DEST_FORMAT__SHIFT); /* Make sure we stay in offsetx field. */ BUG_ON(offset & 0xfffff000); *cmds++ = offset; *cmds++ = cp_type3_packet(CP_SET_CONSTANT, 2); *cmds++ = CP_REG(REG_RB_MODECONTROL); *cmds++ = 0x6; /* EDRAM copy */ *cmds++ = cp_type3_packet(CP_SET_CONSTANT, 2); *cmds++ = CP_REG(REG_PA_CL_CLIP_CNTL); *cmds++ = 0x00010000; if (adreno_is_a22x(adreno_dev)) { *cmds++ = cp_type3_packet(CP_SET_DRAW_INIT_FLAGS, 1); *cmds++ = 0; *cmds++ = cp_type3_packet(CP_SET_CONSTANT, 2); *cmds++ = CP_REG(REG_A220_RB_LRZ_VSC_CONTROL); *cmds++ = 0x0000000; *cmds++ = cp_type3_packet(CP_DRAW_INDX, 3); *cmds++ = 0; /* viz query info. */ /* PrimType=RectList, SrcSel=AutoIndex, VisCullMode=Ignore*/ *cmds++ = 0x00004088; *cmds++ = 3; /* NumIndices=3 */ } else { /* queue the draw packet */ *cmds++ = cp_type3_packet(CP_DRAW_INDX, 2); *cmds++ = 0; /* viz query info. */ /* PrimType=RectList, NumIndices=3, SrcSel=AutoIndex */ *cmds++ = 0x00030088; } /* create indirect buffer command for above command sequence */ create_ib1(drawctxt, shadow->gmem_save, start, cmds); return cmds; }
static void build_shader_save_restore_cmds(struct adreno_device *adreno_dev, struct adreno_context *drawctxt) { unsigned int *cmd = tmp_ctx.cmd; unsigned int *save, *restore, *fixup; unsigned int *startSizeVtx, *startSizePix, *startSizeShared; unsigned int *partition1; unsigned int *shaderBases, *partition2; /* compute vertex, pixel and shared instruction shadow GPU addresses */ tmp_ctx.shader_vertex = drawctxt->gpustate.gpuaddr + SHADER_OFFSET; tmp_ctx.shader_pixel = tmp_ctx.shader_vertex + _shader_shadow_size(adreno_dev); tmp_ctx.shader_shared = tmp_ctx.shader_pixel + _shader_shadow_size(adreno_dev); /* restore shader partitioning and instructions */ restore = cmd; /* start address */ /* Invalidate Vertex & Pixel instruction code address and sizes */ *cmd++ = cp_type3_packet(CP_INVALIDATE_STATE, 1); *cmd++ = 0x00000300; /* 0x100 = Vertex, 0x200 = Pixel */ /* Restore previous shader vertex & pixel instruction bases. */ *cmd++ = cp_type3_packet(CP_SET_SHADER_BASES, 1); shaderBases = cmd++; /* TBD #5: shader bases (from fixup) */ /* write the shader partition information to a scratch register */ *cmd++ = cp_type0_packet(REG_SQ_INST_STORE_MANAGMENT, 1); partition1 = cmd++; /* TBD #4a: partition info (from save) */ /* load vertex shader instructions from the shadow. */ *cmd++ = cp_type3_packet(CP_IM_LOAD, 2); *cmd++ = tmp_ctx.shader_vertex + 0x0; /* 0x0 = Vertex */ startSizeVtx = cmd++; /* TBD #1: start/size (from save) */ /* load pixel shader instructions from the shadow. */ *cmd++ = cp_type3_packet(CP_IM_LOAD, 2); *cmd++ = tmp_ctx.shader_pixel + 0x1; /* 0x1 = Pixel */ startSizePix = cmd++; /* TBD #2: start/size (from save) */ /* load shared shader instructions from the shadow. */ *cmd++ = cp_type3_packet(CP_IM_LOAD, 2); *cmd++ = tmp_ctx.shader_shared + 0x2; /* 0x2 = Shared */ startSizeShared = cmd++; /* TBD #3: start/size (from save) */ /* create indirect buffer command for above command sequence */ create_ib1(drawctxt, drawctxt->shader_restore, restore, cmd); /* * fixup SET_SHADER_BASES data * * since self-modifying PM4 code is being used here, a seperate * command buffer is used for this fixup operation, to ensure the * commands are not read by the PM4 engine before the data fields * have been written. */ fixup = cmd; /* start address */ /* write the shader partition information to a scratch register */ *cmd++ = cp_type0_packet(REG_SCRATCH_REG2, 1); partition2 = cmd++; /* TBD #4b: partition info (from save) */ /* mask off unused bits, then OR with shader instruction memory size */ *cmd++ = cp_type3_packet(CP_REG_RMW, 3); *cmd++ = REG_SCRATCH_REG2; /* AND off invalid bits. */ *cmd++ = 0x0FFF0FFF; /* OR in instruction memory size. */ *cmd++ = adreno_encode_istore_size(adreno_dev); /* write the computed value to the SET_SHADER_BASES data field */ *cmd++ = cp_type3_packet(CP_REG_TO_MEM, 2); *cmd++ = REG_SCRATCH_REG2; /* TBD #5: shader bases (to restore) */ *cmd++ = virt2gpu(shaderBases, &drawctxt->gpustate); /* create indirect buffer command for above command sequence */ create_ib1(drawctxt, drawctxt->shader_fixup, fixup, cmd); /* save shader partitioning and instructions */ save = cmd; /* start address */ *cmd++ = cp_type3_packet(CP_WAIT_FOR_IDLE, 1); *cmd++ = 0; /* fetch the SQ_INST_STORE_MANAGMENT register value, * store the value in the data fields of the SET_CONSTANT commands * above. */ *cmd++ = cp_type3_packet(CP_REG_TO_MEM, 2); *cmd++ = REG_SQ_INST_STORE_MANAGMENT; /* TBD #4a: partition info (to restore) */ *cmd++ = virt2gpu(partition1, &drawctxt->gpustate); *cmd++ = cp_type3_packet(CP_REG_TO_MEM, 2); *cmd++ = REG_SQ_INST_STORE_MANAGMENT; /* TBD #4b: partition info (to fixup) */ *cmd++ = virt2gpu(partition2, &drawctxt->gpustate); /* store the vertex shader instructions */ *cmd++ = cp_type3_packet(CP_IM_STORE, 2); *cmd++ = tmp_ctx.shader_vertex + 0x0; /* 0x0 = Vertex */ /* TBD #1: start/size (to restore) */ *cmd++ = virt2gpu(startSizeVtx, &drawctxt->gpustate); /* store the pixel shader instructions */ *cmd++ = cp_type3_packet(CP_IM_STORE, 2); *cmd++ = tmp_ctx.shader_pixel + 0x1; /* 0x1 = Pixel */ /* TBD #2: start/size (to restore) */ *cmd++ = virt2gpu(startSizePix, &drawctxt->gpustate); /* store the shared shader instructions if vertex base is nonzero */ *cmd++ = cp_type3_packet(CP_IM_STORE, 2); *cmd++ = tmp_ctx.shader_shared + 0x2; /* 0x2 = Shared */ /* TBD #3: start/size (to restore) */ *cmd++ = virt2gpu(startSizeShared, &drawctxt->gpustate); *cmd++ = cp_type3_packet(CP_WAIT_FOR_IDLE, 1); *cmd++ = 0; /* create indirect buffer command for above command sequence */ create_ib1(drawctxt, drawctxt->shader_save, save, cmd); tmp_ctx.cmd = cmd; }
static unsigned int *build_sys2gmem_cmds(struct adreno_device *adreno_dev, struct adreno_context *drawctxt, struct gmem_shadow_t *shadow) { unsigned int *cmds = shadow->gmem_restore_commands; unsigned int *start = cmds; if (!(drawctxt->flags & CTXT_FLAGS_PREAMBLE)) { *cmds++ = cp_type3_packet(CP_REG_TO_MEM, 2); *cmds++ = REG_TP0_CHICKEN; *cmds++ = tmp_ctx.chicken_restore; *cmds++ = cp_type3_packet(CP_WAIT_FOR_IDLE, 1); *cmds++ = 0; } *cmds++ = cp_type0_packet(REG_TP0_CHICKEN, 1); *cmds++ = 0x00000000; *cmds++ = cp_type0_packet(REG_PA_SC_AA_CONFIG, 1); *cmds++ = 0x00000000; *cmds++ = cp_type3_packet(CP_SET_CONSTANT, 7); *cmds++ = (0x1 << 16) | (9 * 6); *cmds++ = shadow->quad_vertices.gpuaddr | 0x3; *cmds++ = 0x00000030; *cmds++ = shadow->quad_texcoords.gpuaddr | 0x3; *cmds++ = 0x00000020; *cmds++ = 0; *cmds++ = 0; *cmds++ = cp_type0_packet(REG_TC_CNTL_STATUS, 1); *cmds++ = 0x1; cmds = program_shader(cmds, 0, sys2gmem_vtx_pgm, SYS2GMEM_VTX_PGM_LEN); *cmds++ = cp_type0_packet(REG_SQ_INST_STORE_MANAGMENT, 1); *cmds++ = adreno_dev->pix_shader_start; *cmds++ = cp_type3_packet(CP_INVALIDATE_STATE, 1); *cmds++ = 0x00000300; *cmds++ = cp_type3_packet(CP_SET_SHADER_BASES, 1); *cmds++ = adreno_encode_istore_size(adreno_dev) | adreno_dev->pix_shader_start; cmds = program_shader(cmds, 1, sys2gmem_frag_pgm, SYS2GMEM_FRAG_PGM_LEN); *cmds++ = cp_type3_packet(CP_SET_CONSTANT, 3); *cmds++ = CP_REG(REG_SQ_PROGRAM_CNTL); *cmds++ = 0x10030002; *cmds++ = 0x00000008; *cmds++ = cp_type3_packet(CP_SET_CONSTANT, 2); *cmds++ = CP_REG(REG_PA_SC_AA_MASK); *cmds++ = 0x0000ffff; if (!adreno_is_a22x(adreno_dev)) { *cmds++ = cp_type3_packet(CP_SET_CONSTANT, 2); *cmds++ = CP_REG(REG_PA_SC_VIZ_QUERY); *cmds++ = 0x0; } *cmds++ = cp_type3_packet(CP_SET_CONSTANT, 2); *cmds++ = CP_REG(REG_RB_COLORCONTROL); *cmds++ = 0x00000c20; *cmds++ = cp_type3_packet(CP_SET_CONSTANT, 4); *cmds++ = CP_REG(REG_VGT_MAX_VTX_INDX); *cmds++ = 0x00ffffff; *cmds++ = 0x0; *cmds++ = 0x00000000; *cmds++ = cp_type3_packet(CP_SET_CONSTANT, 3); *cmds++ = CP_REG(REG_VGT_VERTEX_REUSE_BLOCK_CNTL); *cmds++ = 0x00000002; *cmds++ = 0x00000002; *cmds++ = cp_type3_packet(CP_SET_CONSTANT, 2); *cmds++ = CP_REG(REG_SQ_INTERPOLATOR_CNTL); *cmds++ = 0xffffffff; *cmds++ = cp_type3_packet(CP_SET_CONSTANT, 2); *cmds++ = CP_REG(REG_PA_SC_AA_CONFIG); *cmds++ = 0x00000000; *cmds++ = cp_type3_packet(CP_SET_CONSTANT, 2); *cmds++ = CP_REG(REG_PA_SU_SC_MODE_CNTL); *cmds++ = 0x00080240; *cmds++ = cp_type3_packet(CP_SET_CONSTANT, (SYS2GMEM_TEX_CONST_LEN + 1)); *cmds++ = (0x1 << 16) | (0 * 6); memcpy(cmds, sys2gmem_tex_const, SYS2GMEM_TEX_CONST_LEN << 2); cmds[0] |= (shadow->pitch >> 5) << 22; cmds[1] |= shadow->gmemshadow.gpuaddr | surface_format_table[shadow->format]; cmds[2] |= (shadow->width - 1) | (shadow->height - 1) << 13; cmds += SYS2GMEM_TEX_CONST_LEN; *cmds++ = cp_type3_packet(CP_SET_CONSTANT, 3); *cmds++ = CP_REG(REG_RB_SURFACE_INFO); *cmds++ = shadow->gmem_pitch; *cmds++ = (shadow-> format << RB_COLOR_INFO__COLOR_FORMAT__SHIFT) | tmp_ctx.gmem_base; *cmds++ = cp_type3_packet(CP_SET_CONSTANT, 2); *cmds++ = CP_REG(REG_RB_DEPTHCONTROL); if (adreno_is_a22x(adreno_dev)) *cmds++ = 8; else *cmds++ = 0; *cmds++ = cp_type3_packet(CP_SET_CONSTANT, 3); *cmds++ = CP_REG(REG_PA_SC_SCREEN_SCISSOR_TL); *cmds++ = (0 << 16) | 0; *cmds++ = ((0x1fff) << 16) | 0x1fff; *cmds++ = cp_type3_packet(CP_SET_CONSTANT, 3); *cmds++ = CP_REG(REG_PA_SC_WINDOW_SCISSOR_TL); *cmds++ = (unsigned int)((1U << 31) | (0 << 16) | 0); *cmds++ = ((0x1fff) << 16) | 0x1fff; *cmds++ = cp_type3_packet(CP_SET_CONSTANT, 2); *cmds++ = CP_REG(REG_PA_CL_VTE_CNTL); *cmds++ = 0x00000b00; *cmds++ = cp_type3_packet(CP_SET_CONSTANT, 3); *cmds++ = CP_REG(REG_PA_CL_VPORT_ZSCALE); *cmds++ = 0xbf800000; *cmds++ = 0x0; *cmds++ = cp_type3_packet(CP_SET_CONSTANT, 2); *cmds++ = CP_REG(REG_RB_COLOR_MASK); *cmds++ = 0x0000000f; *cmds++ = cp_type3_packet(CP_SET_CONSTANT, 2); *cmds++ = CP_REG(REG_RB_COLOR_DEST_MASK); *cmds++ = 0xffffffff; *cmds++ = cp_type3_packet(CP_SET_CONSTANT, 3); *cmds++ = CP_REG(REG_SQ_WRAPPING_0); *cmds++ = 0x00000000; *cmds++ = 0x00000000; *cmds++ = cp_type3_packet(CP_SET_CONSTANT, 2); *cmds++ = CP_REG(REG_RB_MODECONTROL); *cmds++ = 0x4; *cmds++ = cp_type3_packet(CP_SET_CONSTANT, 2); *cmds++ = CP_REG(REG_PA_CL_CLIP_CNTL); *cmds++ = 0x00010000; if (adreno_is_a22x(adreno_dev)) { *cmds++ = cp_type3_packet(CP_SET_CONSTANT, 2); *cmds++ = CP_REG(REG_A220_RB_LRZ_VSC_CONTROL); *cmds++ = 0x0000000; *cmds++ = cp_type3_packet(CP_DRAW_INDX, 3); *cmds++ = 0; *cmds++ = 0x00004088; *cmds++ = 3; } else { *cmds++ = cp_type3_packet(CP_DRAW_INDX, 2); *cmds++ = 0; *cmds++ = 0x00030088; } create_ib1(drawctxt, shadow->gmem_restore, start, cmds); return cmds; }
static unsigned int *build_gmem2sys_cmds(struct adreno_device *adreno_dev, struct adreno_context *drawctxt, struct gmem_shadow_t *shadow) { unsigned int *cmds = shadow->gmem_save_commands; unsigned int *start = cmds; unsigned int bytesperpixel = format2bytesperpixel[shadow->format]; unsigned int addr = shadow->gmemshadow.gpuaddr; unsigned int offset = (addr - (addr & 0xfffff000)) / bytesperpixel; if (!(drawctxt->flags & CTXT_FLAGS_PREAMBLE)) { *cmds++ = cp_type3_packet(CP_REG_TO_MEM, 2); *cmds++ = REG_TP0_CHICKEN; *cmds++ = tmp_ctx.chicken_restore; *cmds++ = cp_type3_packet(CP_WAIT_FOR_IDLE, 1); *cmds++ = 0; } *cmds++ = cp_type0_packet(REG_TP0_CHICKEN, 1); *cmds++ = 0x00000000; *cmds++ = cp_type0_packet(REG_PA_SC_AA_CONFIG, 1); *cmds++ = 0x00000000; *cmds++ = cp_type3_packet(CP_SET_CONSTANT, 4); *cmds++ = (0x1 << 16) | SHADER_CONST_ADDR; *cmds++ = 0; *cmds++ = shadow->quad_vertices.gpuaddr | 0x3; *cmds++ = 0x00000030; *cmds++ = cp_type0_packet(REG_TC_CNTL_STATUS, 1); *cmds++ = 0x1; *cmds++ = cp_type3_packet(CP_SET_CONSTANT, 4); *cmds++ = CP_REG(REG_VGT_MAX_VTX_INDX); *cmds++ = 0x00ffffff; *cmds++ = 0x0; *cmds++ = 0x00000000; *cmds++ = cp_type3_packet(CP_SET_CONSTANT, 2); *cmds++ = CP_REG(REG_PA_SC_AA_MASK); *cmds++ = 0x0000ffff; *cmds++ = cp_type3_packet(CP_SET_CONSTANT, 2); *cmds++ = CP_REG(REG_RB_COLORCONTROL); *cmds++ = 0x00000c20; *cmds++ = cp_type0_packet(REG_SQ_INST_STORE_MANAGMENT, 1); *cmds++ = adreno_dev->pix_shader_start; *cmds++ = cp_type3_packet(CP_INVALIDATE_STATE, 1); *cmds++ = 0x00003F00; *cmds++ = cp_type3_packet(CP_SET_SHADER_BASES, 1); *cmds++ = adreno_encode_istore_size(adreno_dev) | adreno_dev->pix_shader_start; cmds = program_shader(cmds, 0, gmem2sys_vtx_pgm, GMEM2SYS_VTX_PGM_LEN); cmds = program_shader(cmds, 1, gmem2sys_frag_pgm, GMEM2SYS_FRAG_PGM_LEN); *cmds++ = cp_type3_packet(CP_SET_CONSTANT, 3); *cmds++ = CP_REG(REG_SQ_PROGRAM_CNTL); if (adreno_is_a22x(adreno_dev)) *cmds++ = 0x10018001; else *cmds++ = 0x10010001; *cmds++ = 0x00000008; *cmds++ = cp_type3_packet(CP_SET_CONSTANT, 2); *cmds++ = CP_REG(REG_PA_CL_VTE_CNTL); *cmds++ = 0x00000b00; *cmds++ = cp_type3_packet(CP_SET_CONSTANT, 3); *cmds++ = CP_REG(REG_RB_SURFACE_INFO); *cmds++ = shadow->gmem_pitch; BUG_ON(tmp_ctx.gmem_base & 0xFFF); *cmds++ = (shadow-> format << RB_COLOR_INFO__COLOR_FORMAT__SHIFT) | tmp_ctx.gmem_base; *cmds++ = cp_type3_packet(CP_SET_CONSTANT, 2); *cmds++ = CP_REG(REG_RB_DEPTHCONTROL); if (adreno_is_a22x(adreno_dev)) *cmds++ = 0x08; else *cmds++ = 0; *cmds++ = cp_type3_packet(CP_SET_CONSTANT, 2); *cmds++ = CP_REG(REG_PA_SU_SC_MODE_CNTL); *cmds++ = 0x00080240; *cmds++ = cp_type3_packet(CP_SET_CONSTANT, 3); *cmds++ = CP_REG(REG_PA_SC_SCREEN_SCISSOR_TL); *cmds++ = (0 << 16) | 0; *cmds++ = (0x1fff << 16) | (0x1fff); *cmds++ = cp_type3_packet(CP_SET_CONSTANT, 3); *cmds++ = CP_REG(REG_PA_SC_WINDOW_SCISSOR_TL); *cmds++ = (unsigned int)((1U << 31) | (0 << 16) | 0); *cmds++ = (0x1fff << 16) | (0x1fff); *cmds++ = cp_type3_packet(CP_SET_CONSTANT, 3); *cmds++ = CP_REG(REG_PA_CL_VPORT_ZSCALE); *cmds++ = 0xbf800000; *cmds++ = 0x0; *cmds++ = cp_type3_packet(CP_SET_CONSTANT, 2); *cmds++ = CP_REG(REG_RB_COLOR_MASK); *cmds++ = 0x0000000f; *cmds++ = cp_type3_packet(CP_SET_CONSTANT, 2); *cmds++ = CP_REG(REG_RB_COLOR_DEST_MASK); *cmds++ = 0xffffffff; *cmds++ = cp_type3_packet(CP_SET_CONSTANT, 3); *cmds++ = CP_REG(REG_SQ_WRAPPING_0); *cmds++ = 0x00000000; *cmds++ = 0x00000000; *cmds++ = cp_type3_packet(CP_SET_CONSTANT, 6); *cmds++ = CP_REG(REG_RB_COPY_CONTROL); *cmds++ = 0; *cmds++ = addr & 0xfffff000; *cmds++ = shadow->pitch >> 5; *cmds++ = 0x0003c008 | (shadow->format << RB_COPY_DEST_INFO__COPY_DEST_FORMAT__SHIFT); BUG_ON(offset & 0xfffff000); *cmds++ = offset; *cmds++ = cp_type3_packet(CP_SET_CONSTANT, 2); *cmds++ = CP_REG(REG_RB_MODECONTROL); *cmds++ = 0x6; *cmds++ = cp_type3_packet(CP_SET_CONSTANT, 2); *cmds++ = CP_REG(REG_PA_CL_CLIP_CNTL); *cmds++ = 0x00010000; if (adreno_is_a22x(adreno_dev)) { *cmds++ = cp_type3_packet(CP_SET_CONSTANT, 2); *cmds++ = CP_REG(REG_A220_RB_LRZ_VSC_CONTROL); *cmds++ = 0x0000000; *cmds++ = cp_type3_packet(CP_DRAW_INDX, 3); *cmds++ = 0; *cmds++ = 0x00004088; *cmds++ = 3; } else { *cmds++ = cp_type3_packet(CP_DRAW_INDX, 2); *cmds++ = 0; *cmds++ = 0x00030088; } create_ib1(drawctxt, shadow->gmem_save, start, cmds); return cmds; }
static void build_shader_save_restore_cmds(struct adreno_device *adreno_dev, struct adreno_context *drawctxt) { unsigned int *cmd = tmp_ctx.cmd; unsigned int *save, *restore, *fixup; unsigned int *startSizeVtx, *startSizePix, *startSizeShared; unsigned int *partition1; unsigned int *shaderBases, *partition2; tmp_ctx.shader_vertex = drawctxt->gpustate.gpuaddr + SHADER_OFFSET; tmp_ctx.shader_pixel = tmp_ctx.shader_vertex + _shader_shadow_size(adreno_dev); tmp_ctx.shader_shared = tmp_ctx.shader_pixel + _shader_shadow_size(adreno_dev); restore = cmd; *cmd++ = cp_type3_packet(CP_INVALIDATE_STATE, 1); *cmd++ = 0x00000300; *cmd++ = cp_type3_packet(CP_SET_SHADER_BASES, 1); shaderBases = cmd++; *cmd++ = cp_type0_packet(REG_SQ_INST_STORE_MANAGMENT, 1); partition1 = cmd++; *cmd++ = cp_type3_packet(CP_IM_LOAD, 2); *cmd++ = tmp_ctx.shader_vertex + 0x0; startSizeVtx = cmd++; *cmd++ = cp_type3_packet(CP_IM_LOAD, 2); *cmd++ = tmp_ctx.shader_pixel + 0x1; startSizePix = cmd++; *cmd++ = cp_type3_packet(CP_IM_LOAD, 2); *cmd++ = tmp_ctx.shader_shared + 0x2; startSizeShared = cmd++; create_ib1(drawctxt, drawctxt->shader_restore, restore, cmd); /* * fixup SET_SHADER_BASES data * * since self-modifying PM4 code is being used here, a seperate * command buffer is used for this fixup operation, to ensure the * commands are not read by the PM4 engine before the data fields * have been written. */ fixup = cmd; *cmd++ = cp_type0_packet(REG_SCRATCH_REG2, 1); partition2 = cmd++; *cmd++ = cp_type3_packet(CP_REG_RMW, 3); *cmd++ = REG_SCRATCH_REG2; *cmd++ = 0x0FFF0FFF; *cmd++ = adreno_encode_istore_size(adreno_dev); *cmd++ = cp_type3_packet(CP_REG_TO_MEM, 2); *cmd++ = REG_SCRATCH_REG2; *cmd++ = virt2gpu(shaderBases, &drawctxt->gpustate); create_ib1(drawctxt, drawctxt->shader_fixup, fixup, cmd); save = cmd; *cmd++ = cp_type3_packet(CP_WAIT_FOR_IDLE, 1); *cmd++ = 0; *cmd++ = cp_type3_packet(CP_REG_TO_MEM, 2); *cmd++ = REG_SQ_INST_STORE_MANAGMENT; *cmd++ = virt2gpu(partition1, &drawctxt->gpustate); *cmd++ = cp_type3_packet(CP_REG_TO_MEM, 2); *cmd++ = REG_SQ_INST_STORE_MANAGMENT; *cmd++ = virt2gpu(partition2, &drawctxt->gpustate); *cmd++ = cp_type3_packet(CP_IM_STORE, 2); *cmd++ = tmp_ctx.shader_vertex + 0x0; *cmd++ = virt2gpu(startSizeVtx, &drawctxt->gpustate); *cmd++ = cp_type3_packet(CP_IM_STORE, 2); *cmd++ = tmp_ctx.shader_pixel + 0x1; *cmd++ = virt2gpu(startSizePix, &drawctxt->gpustate); *cmd++ = cp_type3_packet(CP_IM_STORE, 2); *cmd++ = tmp_ctx.shader_shared + 0x2; *cmd++ = virt2gpu(startSizeShared, &drawctxt->gpustate); *cmd++ = cp_type3_packet(CP_WAIT_FOR_IDLE, 1); *cmd++ = 0; create_ib1(drawctxt, drawctxt->shader_save, save, cmd); tmp_ctx.cmd = cmd; }