static int pcl725_attach(struct comedi_device *dev, struct comedi_devconfig *it) { struct comedi_subdevice *s; unsigned long iobase; iobase = it->options[0]; printk("comedi%d: pcl725: 0x%04lx ", dev->minor, iobase); if (!request_region(iobase, PCL725_SIZE, "pcl725")) { printk("I/O port conflict\n"); return -EIO; } dev->board_name = "pcl725"; dev->iobase = iobase; dev->irq = 0; if (alloc_subdevices(dev, 2) < 0) return -ENOMEM; s = dev->subdevices + 0; /* do */ s->type = COMEDI_SUBD_DO; s->subdev_flags = SDF_WRITABLE; s->maxdata = 1; s->n_chan = 8; s->insn_bits = pcl725_do_insn; s->range_table = &range_digital; s = dev->subdevices + 1; /* di */ s->type = COMEDI_SUBD_DI; s->subdev_flags = SDF_READABLE; s->maxdata = 1; s->n_chan = 8; s->insn_bits = pcl725_di_insn; s->range_table = &range_digital; printk("\n"); return 0; }
static int nidio_attach(struct comedi_device *dev, struct comedi_devconfig *it) { struct comedi_subdevice *s; int i; int ret; int n_subdevices; unsigned int irq; printk("comedi%d: nidio:", dev->minor); if ((ret = alloc_private(dev, sizeof(struct nidio96_private))) < 0) return ret; spin_lock_init(&devpriv->mite_channel_lock); ret = nidio_find_device(dev, it->options[0], it->options[1]); if (ret < 0) return ret; ret = mite_setup(devpriv->mite); if (ret < 0) { printk("error setting up mite\n"); return ret; } comedi_set_hw_dev(dev, &devpriv->mite->pcidev->dev); devpriv->di_mite_ring = mite_alloc_ring(devpriv->mite); if (devpriv->di_mite_ring == NULL) return -ENOMEM; dev->board_name = this_board->name; irq = mite_irq(devpriv->mite); printk(" %s", dev->board_name); if (this_board->uses_firmware) { ret = pci_6534_upload_firmware(dev, it->options); if (ret < 0) return ret; } if (!this_board->is_diodaq) { n_subdevices = this_board->n_8255; } else { n_subdevices = 1; } if ((ret = alloc_subdevices(dev, n_subdevices)) < 0) return ret; if (!this_board->is_diodaq) { for (i = 0; i < this_board->n_8255; i++) { subdev_8255_init(dev, dev->subdevices + i, nidio96_8255_cb, (unsigned long)(devpriv->mite-> daq_io_addr + NIDIO_8255_BASE(i))); } } else { printk(" rev=%d", readb(devpriv->mite->daq_io_addr + Chip_Version)); s = dev->subdevices + 0; dev->read_subdev = s; s->type = COMEDI_SUBD_DIO; s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_LSAMPL | SDF_PACKED | SDF_CMD_READ; s->n_chan = 32; s->range_table = &range_digital; s->maxdata = 1; s->insn_config = &ni_pcidio_insn_config; s->insn_bits = &ni_pcidio_insn_bits; s->do_cmd = &ni_pcidio_cmd; s->do_cmdtest = &ni_pcidio_cmdtest; s->cancel = &ni_pcidio_cancel; s->len_chanlist = 32; s->buf_change = &ni_pcidio_change; s->async_dma_dir = DMA_BIDIRECTIONAL; writel(0, devpriv->mite->daq_io_addr + Port_IO(0)); writel(0, devpriv->mite->daq_io_addr + Port_Pin_Directions(0)); writel(0, devpriv->mite->daq_io_addr + Port_Pin_Mask(0)); writeb(0x00, devpriv->mite->daq_io_addr + Master_DMA_And_Interrupt_Control); ret = request_irq(irq, nidio_interrupt, IRQF_SHARED, "ni_pcidio", dev); if (ret < 0) { printk(" irq not available"); } dev->irq = irq; } printk("\n"); return 0; }
static int multiq3_attach(struct comedi_device *dev, struct comedi_devconfig *it) { int result = 0; unsigned long iobase; unsigned int irq; struct comedi_subdevice *s; iobase = it->options[0]; printk("comedi%d: multiq3: 0x%04lx ", dev->minor, iobase); if (!request_region(iobase, MULTIQ3_SIZE, "multiq3")) { printk("comedi%d: I/O port conflict\n", dev->minor); return -EIO; } dev->iobase = iobase; irq = it->options[1]; if (irq) { printk("comedi%d: irq = %u ignored\n", dev->minor, irq); } else { printk("comedi%d: no irq\n", dev->minor); } dev->board_name = "multiq3"; result = alloc_subdevices(dev, 5); if (result < 0) return result; result = alloc_private(dev, sizeof(struct multiq3_private)); if (result < 0) return result; s = dev->subdevices + 0; /* ai subdevice */ s->type = COMEDI_SUBD_AI; s->subdev_flags = SDF_READABLE | SDF_GROUND; s->n_chan = 8; s->insn_read = multiq3_ai_insn_read; s->maxdata = 0x1fff; s->range_table = &range_bipolar5; s = dev->subdevices + 1; /* ao subdevice */ s->type = COMEDI_SUBD_AO; s->subdev_flags = SDF_WRITABLE; s->n_chan = 8; s->insn_read = multiq3_ao_insn_read; s->insn_write = multiq3_ao_insn_write; s->maxdata = 0xfff; s->range_table = &range_bipolar5; s = dev->subdevices + 2; /* di subdevice */ s->type = COMEDI_SUBD_DI; s->subdev_flags = SDF_READABLE; s->n_chan = 16; s->insn_bits = multiq3_di_insn_bits; s->maxdata = 1; s->range_table = &range_digital; s = dev->subdevices + 3; /* do subdevice */ s->type = COMEDI_SUBD_DO; s->subdev_flags = SDF_WRITABLE; s->n_chan = 16; s->insn_bits = multiq3_do_insn_bits; s->maxdata = 1; s->range_table = &range_digital; s->state = 0; s = dev->subdevices + 4; /* encoder (counter) subdevice */ s->type = COMEDI_SUBD_COUNTER; s->subdev_flags = SDF_READABLE | SDF_LSAMPL; s->n_chan = it->options[2] * 2; s->insn_read = multiq3_encoder_insn_read; s->maxdata = 0xffffff; s->range_table = &range_unknown; encoder_reset(dev); return 0; }
static int adl_pci8164_attach(comedi_device * dev, comedi_devconfig * it) { struct pci_dev *pcidev; comedi_subdevice *s; int bus, slot; printk("comedi: attempt to attach...\n"); printk("comedi%d: adl_pci8164\n", dev->minor); dev->board_name = "pci8164"; bus = it->options[0]; slot = it->options[1]; if (alloc_private(dev, sizeof(adl_pci8164_private)) < 0) return -ENOMEM; if (alloc_subdevices(dev, 4) < 0) return -ENOMEM; for (pcidev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, NULL); pcidev != NULL; pcidev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, pcidev)) { if (pcidev->vendor == PCI_VENDOR_ID_ADLINK && pcidev->device == PCI_DEVICE_ID_PCI8164) { if (bus || slot) { /* requested particular bus/slot */ if (pcidev->bus->number != bus || PCI_SLOT(pcidev->devfn) != slot) { continue; } } devpriv->pci_dev = pcidev; if (comedi_pci_enable(pcidev, "adl_pci8164") < 0) { printk("comedi%d: Failed to enable PCI device and request regions\n", dev->minor); return -EIO; } dev->iobase = pci_resource_start(pcidev, 2); printk("comedi: base addr %4lx\n", dev->iobase); s = dev->subdevices + 0; s->type = COMEDI_SUBD_PROC; s->subdev_flags = SDF_READABLE | SDF_WRITABLE; s->n_chan = 4; s->maxdata = 0xffff; s->len_chanlist = 4; //s->range_table = &range_axis; s->insn_read = adl_pci8164_insn_read_msts; s->insn_write = adl_pci8164_insn_write_cmd; s = dev->subdevices + 1; s->type = COMEDI_SUBD_PROC; s->subdev_flags = SDF_READABLE | SDF_WRITABLE; s->n_chan = 4; s->maxdata = 0xffff; s->len_chanlist = 4; //s->range_table = &range_axis; s->insn_read = adl_pci8164_insn_read_ssts; s->insn_write = adl_pci8164_insn_write_otp; s = dev->subdevices + 2; s->type = COMEDI_SUBD_PROC; s->subdev_flags = SDF_READABLE | SDF_WRITABLE; s->n_chan = 4; s->maxdata = 0xffff; s->len_chanlist = 4; //s->range_table = &range_axis; s->insn_read = adl_pci8164_insn_read_buf0; s->insn_write = adl_pci8164_insn_write_buf0; s = dev->subdevices + 3; s->type = COMEDI_SUBD_PROC; s->subdev_flags = SDF_READABLE | SDF_WRITABLE; s->n_chan = 4; s->maxdata = 0xffff; s->len_chanlist = 4; //s->range_table = &range_axis; s->insn_read = adl_pci8164_insn_read_buf1; s->insn_write = adl_pci8164_insn_write_buf1; printk("comedi: attached\n"); return 1; } } printk("comedi%d: no supported board found! (req. bus/slot : %d/%d)\n", dev->minor, bus, slot); return -EIO; }
void i_ADDI_AttachPCI1710(struct comedi_device *dev) { struct comedi_subdevice *s; int ret = 0; int n_subdevices = 9; /* Update-0.7.57->0.7.68dev->n_subdevices = 9; */ ret = alloc_subdevices(dev, n_subdevices); if (ret < 0) return; /* Allocate and Initialise Timer Subdevice Structures */ s = dev->subdevices + 0; s->type = COMEDI_SUBD_TIMER; s->subdev_flags = SDF_WRITEABLE | SDF_GROUND | SDF_COMMON; s->n_chan = 3; s->maxdata = 0; s->len_chanlist = 3; s->range_table = &range_digital; s->insn_write = i_APCI1710_InsnWriteEnableDisableTimer; s->insn_read = i_APCI1710_InsnReadAllTimerValue; s->insn_config = i_APCI1710_InsnConfigInitTimer; s->insn_bits = i_APCI1710_InsnBitsTimer; /* Allocate and Initialise DIO Subdevice Structures */ s = dev->subdevices + 1; s->type = COMEDI_SUBD_DIO; s->subdev_flags = SDF_WRITEABLE | SDF_READABLE | SDF_GROUND | SDF_COMMON; s->n_chan = 7; s->maxdata = 1; s->len_chanlist = 7; s->range_table = &range_digital; s->insn_config = i_APCI1710_InsnConfigDigitalIO; s->insn_read = i_APCI1710_InsnReadDigitalIOChlValue; s->insn_bits = i_APCI1710_InsnBitsDigitalIOPortOnOff; s->insn_write = i_APCI1710_InsnWriteDigitalIOChlOnOff; /* Allocate and Initialise Chrono Subdevice Structures */ s = dev->subdevices + 2; s->type = COMEDI_SUBD_CHRONO; s->subdev_flags = SDF_WRITEABLE | SDF_GROUND | SDF_COMMON; s->n_chan = 4; s->maxdata = 0; s->len_chanlist = 4; s->range_table = &range_digital; s->insn_write = i_APCI1710_InsnWriteEnableDisableChrono; s->insn_read = i_APCI1710_InsnReadChrono; s->insn_config = i_APCI1710_InsnConfigInitChrono; s->insn_bits = i_APCI1710_InsnBitsChronoDigitalIO; /* Allocate and Initialise PWM Subdevice Structures */ s = dev->subdevices + 3; s->type = COMEDI_SUBD_PWM; s->subdev_flags = SDF_WRITEABLE | SDF_READABLE | SDF_GROUND | SDF_COMMON; s->n_chan = 3; s->maxdata = 1; s->len_chanlist = 3; s->range_table = &range_digital; s->io_bits = 0; /* all bits input */ s->insn_config = i_APCI1710_InsnConfigPWM; s->insn_read = i_APCI1710_InsnReadGetPWMStatus; s->insn_write = i_APCI1710_InsnWritePWM; s->insn_bits = i_APCI1710_InsnBitsReadPWMInterrupt; /* Allocate and Initialise TTLIO Subdevice Structures */ s = dev->subdevices + 4; s->type = COMEDI_SUBD_TTLIO; s->subdev_flags = SDF_WRITEABLE | SDF_READABLE | SDF_GROUND | SDF_COMMON; s->n_chan = 8; s->maxdata = 1; s->len_chanlist = 8; s->range_table = &range_apci1710_ttl; /* to pass arguments in range */ s->insn_config = i_APCI1710_InsnConfigInitTTLIO; s->insn_bits = i_APCI1710_InsnBitsReadTTLIO; s->insn_write = i_APCI1710_InsnWriteSetTTLIOChlOnOff; s->insn_read = i_APCI1710_InsnReadTTLIOAllPortValue; /* Allocate and Initialise TOR Subdevice Structures */ s = dev->subdevices + 5; s->type = COMEDI_SUBD_TOR; s->subdev_flags = SDF_WRITEABLE | SDF_READABLE | SDF_GROUND | SDF_COMMON; s->n_chan = 8; s->maxdata = 1; s->len_chanlist = 8; s->range_table = &range_digital; s->io_bits = 0; /* all bits input */ s->insn_config = i_APCI1710_InsnConfigInitTorCounter; s->insn_read = i_APCI1710_InsnReadGetTorCounterInitialisation; s->insn_write = i_APCI1710_InsnWriteEnableDisableTorCounter; s->insn_bits = i_APCI1710_InsnBitsGetTorCounterProgressStatusAndValue; /* Allocate and Initialise SSI Subdevice Structures */ s = dev->subdevices + 6; s->type = COMEDI_SUBD_SSI; s->subdev_flags = SDF_WRITEABLE | SDF_READABLE | SDF_GROUND | SDF_COMMON; s->n_chan = 4; s->maxdata = 1; s->len_chanlist = 4; s->range_table = &range_apci1710_ssi; s->insn_config = i_APCI1710_InsnConfigInitSSI; s->insn_read = i_APCI1710_InsnReadSSIValue; s->insn_bits = i_APCI1710_InsnBitsSSIDigitalIO; /* Allocate and Initialise PULSEENCODER Subdevice Structures */ s = dev->subdevices + 7; s->type = COMEDI_SUBD_PULSEENCODER; s->subdev_flags = SDF_WRITEABLE | SDF_READABLE | SDF_GROUND | SDF_COMMON; s->n_chan = 4; s->maxdata = 1; s->len_chanlist = 4; s->range_table = &range_digital; s->insn_config = i_APCI1710_InsnConfigInitPulseEncoder; s->insn_write = i_APCI1710_InsnWriteEnableDisablePulseEncoder; s->insn_bits = i_APCI1710_InsnBitsReadWritePulseEncoder; s->insn_read = i_APCI1710_InsnReadInterruptPulseEncoder; /* Allocate and Initialise INCREMENTALCOUNTER Subdevice Structures */ s = dev->subdevices + 8; s->type = COMEDI_SUBD_INCREMENTALCOUNTER; s->subdev_flags = SDF_WRITEABLE | SDF_READABLE | SDF_GROUND | SDF_COMMON; s->n_chan = 500; s->maxdata = 1; s->len_chanlist = 500; s->range_table = &range_apci1710_inccpt; s->insn_config = i_APCI1710_InsnConfigINCCPT; s->insn_write = i_APCI1710_InsnWriteINCCPT; s->insn_read = i_APCI1710_InsnReadINCCPT; s->insn_bits = i_APCI1710_InsnBitsINCCPT; }
static int dt2815_attach(struct comedi_device *dev, struct comedi_devconfig *it) { struct comedi_subdevice *s; int i; const struct comedi_lrange *current_range_type, *voltage_range_type; unsigned long iobase; iobase = it->options[0]; printk(KERN_INFO "comedi%d: dt2815: 0x%04lx ", dev->minor, iobase); if (!request_region(iobase, DT2815_SIZE, "dt2815")) { printk(KERN_WARNING "I/O port conflict\n"); return -EIO; } dev->iobase = iobase; dev->board_name = "dt2815"; if (alloc_subdevices(dev, 1) < 0) return -ENOMEM; if (alloc_private(dev, sizeof(struct dt2815_private)) < 0) return -ENOMEM; s = dev->subdevices; /* ao subdevice */ s->type = COMEDI_SUBD_AO; s->subdev_flags = SDF_WRITABLE; s->maxdata = 0xfff; s->n_chan = 8; s->insn_write = dt2815_ao_insn; s->insn_read = dt2815_ao_insn_read; s->range_table_list = devpriv->range_type_list; current_range_type = (it->options[3]) ? &range_dt2815_ao_20_current : &range_dt2815_ao_32_current; voltage_range_type = (it->options[2]) ? &range_bipolar5 : &range_unipolar5; for (i = 0; i < 8; i++) { devpriv->range_type_list[i] = (it->options[5 + i]) ? current_range_type : voltage_range_type; } /* Init the 2815 */ outb(0x00, dev->iobase + DT2815_STATUS); for (i = 0; i < 100; i++) { /* This is incredibly slow (approx 20 ms) */ unsigned int status; udelay(1000); status = inb(dev->iobase + DT2815_STATUS); if (status == 4) { unsigned int program; program = (it->options[4] & 0x3) << 3 | 0x7; outb(program, dev->iobase + DT2815_DATA); printk(KERN_INFO ", program: 0x%x (@t=%d)\n", program, i); break; } else if (status != 0x00) { printk(KERN_WARNING "dt2815: unexpected status 0x%x " "(@t=%d)\n", status, i); if (status & 0x60) outb(0x00, dev->iobase + DT2815_STATUS); } } return 0; }