C++ (Cpp) allocate_register_manually_w Examples

Example #1

File: gspecial.c Project: hoadn/mupen64plus-ae

void genmult(void)
{
#ifdef INTERPRET_MULT
    gencallinterp((unsigned int)cached_interpreter_table.MULT, 0);
#else
    int rs, rt;
    allocate_register_manually_w(EAX, (unsigned int *)&lo, 0);
    allocate_register_manually_w(EDX, (unsigned int *)&hi, 0);
    rs = allocate_register((unsigned int*)dst->f.r.rs);
    rt = allocate_register((unsigned int*)dst->f.r.rt);
    mov_reg32_reg32(EAX, rs);
    imul_reg32(rt);
#endif
}

Example #2

File: gspecial.c Project: GPDP2/mupen64

void genmultu()
{
#ifdef INTERPRET_MULTU
   gencallinterp((unsigned long)MULTU, 0);
#else
   int rs, rt;
   allocate_register_manually_w(EAX, (unsigned long *)&lo, 0);
   allocate_register_manually_w(EDX, (unsigned long *)&hi, 0);
   rs = allocate_register((unsigned long*)dst->f.r.rs);
   rt = allocate_register((unsigned long*)dst->f.r.rt);
   mov_reg32_reg32(EAX, rs);
   mul_reg32(rt);
#endif
}

Example #3

File: gspecial.c Project: derselbst/lazyusf2

void genmultu(usf_state_t * state)
{
#ifdef INTERPRET_MULTU
   gencallinterp(state, (unsigned int)state->current_instruction_table.MULTU, 0);
#else
   int rs, rt;
   allocate_register_manually_w(state, EAX, (unsigned int *)&state->lo, 0);
   allocate_register_manually_w(state, EDX, (unsigned int *)&state->hi, 0);
   rs = allocate_register(state, (unsigned int*)state->dst->f.r.rs);
   rt = allocate_register(state, (unsigned int*)state->dst->f.r.rt);
   mov_reg32_reg32(state, EAX, rs);
   mul_reg32(state, rt);
#endif
}

Example #4

File: gspecial.c Project: krnlyng/mupen64plus-core

void genmultu(void)
{
#ifdef INTERPRET_MULTU
   gencallinterp((unsigned int)cached_interpreter_table.MULTU, 0);
#else
   int rs, rt;
   allocate_register_manually_w(EAX, (unsigned int *)r4300_mult_lo(), 0);
   allocate_register_manually_w(EDX, (unsigned int *)r4300_mult_hi(), 0);
   rs = allocate_register((unsigned int*)g_dev.r4300.recomp.dst->f.r.rs);
   rt = allocate_register((unsigned int*)g_dev.r4300.recomp.dst->f.r.rt);
   mov_reg32_reg32(EAX, rs);
   mul_reg32(rt);
#endif
}

Example #5

File: gspecial.c Project: GPDP2/mupen64

void gendivu()
{
#ifdef INTERPRET_DIVU
   gencallinterp((unsigned long)DIVU, 0);
#else
   int rs, rt;
   allocate_register_manually_w(EAX, (unsigned long *)&lo, 0);
   allocate_register_manually_w(EDX, (unsigned long *)&hi, 0);
   rs = allocate_register((unsigned long*)dst->f.r.rs);
   rt = allocate_register((unsigned long*)dst->f.r.rt);
   cmp_reg32_imm32(rt, 0);
   je_rj((rs == EAX ? 0 : 2) + 2 + 2);
   mov_reg32_reg32(EAX, rs); // 0 or 2
   xor_reg32_reg32(EDX, EDX); // 2
   div_reg32(rt); // 2
#endif
}

Example #6

File: gspecial.c Project: hoadn/mupen64plus-ae

void gendiv(void)
{
#ifdef INTERPRET_DIV
    gencallinterp((unsigned int)cached_interpreter_table.DIV, 0);
#else
    int rs, rt;
    allocate_register_manually_w(EAX, (unsigned int *)&lo, 0);
    allocate_register_manually_w(EDX, (unsigned int *)&hi, 0);
    rs = allocate_register((unsigned int*)dst->f.r.rs);
    rt = allocate_register((unsigned int*)dst->f.r.rt);
    cmp_reg32_imm32(rt, 0);
    je_rj((rs == EAX ? 0 : 2) + 1 + 2);
    mov_reg32_reg32(EAX, rs); // 0 or 2
    cdq(); // 1
    idiv_reg32(rt); // 2
#endif
}

Example #7

File: gspecial.c Project: derselbst/lazyusf2

void gendivu(usf_state_t * state)
{
#ifdef INTERPRET_DIVU
   gencallinterp(state, (unsigned int)state->current_instruction_table.DIVU, 0);
#else
   int rs, rt;
   allocate_register_manually_w(state, EAX, (unsigned int *)&state->lo, 0);
   allocate_register_manually_w(state, EDX, (unsigned int *)&state->hi, 0);
   rs = allocate_register(state, (unsigned int*)state->dst->f.r.rs);
   rt = allocate_register(state, (unsigned int*)state->dst->f.r.rt);
   cmp_reg32_imm32(state, rt, 0);
   je_rj(state, (rs == EAX ? 0 : 2) + 2 + 2);
   mov_reg32_reg32(state, EAX, rs); // 0 or 2
   xor_reg32_reg32(state, EDX, EDX); // 2
   div_reg32(state, rt); // 2
#endif
}

Example #8

File: gspecial.c Project: krnlyng/mupen64plus-core

void gendivu(void)
{
#ifdef INTERPRET_DIVU
   gencallinterp((unsigned int)cached_interpreter_table.DIVU, 0);
#else
   int rs, rt;
   allocate_register_manually_w(EAX, (unsigned int *)r4300_mult_lo(), 0);
   allocate_register_manually_w(EDX, (unsigned int *)r4300_mult_hi(), 0);
   rs = allocate_register((unsigned int*)g_dev.r4300.recomp.dst->f.r.rs);
   rt = allocate_register((unsigned int*)g_dev.r4300.recomp.dst->f.r.rt);
   cmp_reg32_imm32(rt, 0);
   je_rj((rs == EAX ? 0 : 2) + 2 + 2);
   mov_reg32_reg32(EAX, rs); // 0 or 2
   xor_reg32_reg32(EDX, EDX); // 2
   div_reg32(rt); // 2
#endif
}