void
jensenio_intr_init(struct jensenio_config *jcp)
{
eisa_chipset_tag_t ec = &jcp->jc_ec;
isa_chipset_tag_t ic = &jcp->jc_ic;
char *cp;
int i;
pic_iot = &jcp->jc_eisa_iot;
jensenio_pic_init();
jensenio_eisa_intr = alpha_shared_intr_alloc(JENSEN_MAX_IRQ, 16);
for (i = 0; i < JENSEN_MAX_IRQ; i++) {
alpha_shared_intr_set_dfltsharetype(jensenio_eisa_intr,
i, jensenio_intr_deftype[i]);
/* Don't bother with stray interrupts. */
alpha_shared_intr_set_maxstrays(jensenio_eisa_intr,
i, 0);
cp = alpha_shared_intr_string(jensenio_eisa_intr, i);
sprintf(cp, "irq %d", i);
evcnt_attach_dynamic(alpha_shared_intr_evcnt(
jensenio_eisa_intr, i), EVCNT_TYPE_INTR,
NULL, "eisa", cp);
}
/*
* The cascasde interrupt must be edge triggered and always enabled.
*/
jensenio_setlevel(2, 0);
jensenio_enable_intr(2, 1);
/*
* Initialize the EISA chipset.
*/
ec->ec_v = jcp;
ec->ec_intr_map = jensenio_eisa_intr_map;
ec->ec_intr_string = jensenio_eisa_intr_string;
ec->ec_intr_evcnt = jensenio_eisa_intr_evcnt;
ec->ec_intr_establish = jensenio_eisa_intr_establish;
ec->ec_intr_disestablish = jensenio_eisa_intr_disestablish;
/*
* Initialize the ISA chipset.
*/
ic->ic_v = jcp;
ic->ic_intr_establish = jensenio_eisa_intr_establish;
ic->ic_intr_disestablish = jensenio_eisa_intr_disestablish;
ic->ic_intr_alloc = jensenio_eisa_intr_alloc;
ic->ic_intr_evcnt = jensenio_eisa_intr_evcnt;
}
void
pci_eb164_pickintr(struct cia_config *ccp)
{
bus_space_tag_t iot = &ccp->cc_iot;
pci_chipset_tag_t pc = &ccp->cc_pc;
char *cp;
int i;
pc->pc_intr_v = ccp;
pc->pc_intr_map = dec_eb164_intr_map;
pc->pc_intr_string = dec_eb164_intr_string;
pc->pc_intr_evcnt = dec_eb164_intr_evcnt;
pc->pc_intr_establish = dec_eb164_intr_establish;
pc->pc_intr_disestablish = dec_eb164_intr_disestablish;
pc->pc_pciide_compat_intr_establish =
dec_eb164_pciide_compat_intr_establish;
eb164_intrgate_iot = iot;
if (bus_space_map(eb164_intrgate_iot, 0x804, 3, 0,
&eb164_intrgate_ioh) != 0)
panic("pci_eb164_pickintr: couldn't map interrupt PLD");
for (i = 0; i < EB164_MAX_IRQ; i++)
eb164_intr_disable(i);
#define PCI_EB164_IRQ_STR 8
eb164_pci_intr = alpha_shared_intr_alloc(EB164_MAX_IRQ,
PCI_EB164_IRQ_STR);
for (i = 0; i < EB164_MAX_IRQ; i++) {
/*
* Systems with a Pyxis seem to have problems with
* stray interrupts, so just ignore them. Sigh,
* I hate buggy hardware.
*/
alpha_shared_intr_set_maxstrays(eb164_pci_intr, i,
(ccp->cc_flags & CCF_ISPYXIS) ? 0 : PCI_STRAY_MAX);
cp = alpha_shared_intr_string(eb164_pci_intr, i);
snprintf(cp, PCI_EB164_IRQ_STR, "irq %d", i);
evcnt_attach_dynamic(alpha_shared_intr_evcnt(
eb164_pci_intr, i), EVCNT_TYPE_INTR, NULL,
"eb164", cp);
}
#if NSIO
sio_intr_setup(pc, iot);
eb164_intr_enable(EB164_SIO_IRQ);
#endif
}
void
pci_eb64plus_pickintr(struct apecs_config *acp)
{
bus_space_tag_t iot = &acp->ac_iot;
pci_chipset_tag_t pc = &acp->ac_pc;
char *cp;
int i;
pc->pc_intr_v = acp;
pc->pc_intr_map = dec_eb64plus_intr_map;
pc->pc_intr_string = dec_eb64plus_intr_string;
pc->pc_intr_evcnt = dec_eb64plus_intr_evcnt;
pc->pc_intr_establish = dec_eb64plus_intr_establish;
pc->pc_intr_disestablish = dec_eb64plus_intr_disestablish;
/* Not supported on the EB64+. */
pc->pc_pciide_compat_intr_establish = NULL;
eb64plus_intrgate_iot = iot;
if (bus_space_map(eb64plus_intrgate_iot, 0x804, 3, 0,
&eb64plus_intrgate_ioh) != 0)
panic("pci_eb64plus_pickintr: couldn't map interrupt PLD");
for (i = 0; i < EB64PLUS_MAX_IRQ; i++)
eb64plus_intr_disable(i);
#define PCI_EB64PLUS_IRQ_STR 8
eb64plus_pci_intr = alpha_shared_intr_alloc(EB64PLUS_MAX_IRQ,
PCI_EB64PLUS_IRQ_STR);
for (i = 0; i < EB64PLUS_MAX_IRQ; i++) {
alpha_shared_intr_set_maxstrays(eb64plus_pci_intr, i,
PCI_STRAY_MAX);
cp = alpha_shared_intr_string(eb64plus_pci_intr, i);
snprintf(cp, PCI_EB64PLUS_IRQ_STR, "irq %d", i);
evcnt_attach_dynamic(alpha_shared_intr_evcnt(
eb64plus_pci_intr, i), EVCNT_TYPE_INTR, NULL,
"eb64+", cp);
}
#if NSIO
sio_intr_setup(pc, iot);
#endif
}
void
pci_550_pickintr(struct cia_config *ccp)
{
bus_space_tag_t iot = &ccp->cc_iot;
pci_chipset_tag_t pc = &ccp->cc_pc;
char *cp;
int i;
pc->pc_intr_v = ccp;
pc->pc_intr_map = dec_550_intr_map;
pc->pc_intr_string = dec_550_intr_string;
pc->pc_intr_evcnt = dec_550_intr_evcnt;
pc->pc_intr_establish = dec_550_intr_establish;
pc->pc_intr_disestablish = dec_550_intr_disestablish;
pc->pc_pciide_compat_intr_establish =
dec_550_pciide_compat_intr_establish;
/*
* DEC 550's interrupts are enabled via the Pyxis interrupt
* mask register. Nothing to map.
*/
for (i = 0; i < DEC_550_MAX_IRQ; i++)
dec_550_intr_disable(i);
dec_550_pci_intr = alpha_shared_intr_alloc(DEC_550_MAX_IRQ, 8);
for (i = 0; i < DEC_550_MAX_IRQ; i++) {
alpha_shared_intr_set_maxstrays(dec_550_pci_intr, i,
PCI_STRAY_MAX);
alpha_shared_intr_set_private(dec_550_pci_intr, i, ccp);
cp = alpha_shared_intr_string(dec_550_pci_intr, i);
sprintf(cp, "irq %d", i);
evcnt_attach_dynamic(alpha_shared_intr_evcnt(
dec_550_pci_intr, i), EVCNT_TYPE_INTR, NULL,
"dec_550", cp);
}
#if NSIO
sio_intr_setup(pc, iot);
#endif
}
void
pci_1000a_pickintr(void *core, bus_space_tag_t iot, bus_space_tag_t memt, pci_chipset_tag_t pc)
{
char *cp;
int i;
mystery_icu_iot = iot;
pc_tag = pc;
if (bus_space_map(iot, 0x54a, 2, 0, mystery_icu_ioh + 0)
|| bus_space_map(iot, 0x54c, 2, 0, mystery_icu_ioh + 1))
panic("pci_1000a_pickintr");
pc->pc_intr_v = core;
pc->pc_intr_map = dec_1000a_intr_map;
pc->pc_intr_string = dec_1000a_intr_string;
pc->pc_intr_evcnt = dec_1000a_intr_evcnt;
pc->pc_intr_establish = dec_1000a_intr_establish;
pc->pc_intr_disestablish = dec_1000a_intr_disestablish;
pc->pc_pciide_compat_intr_establish = NULL;
dec_1000a_pci_intr = alpha_shared_intr_alloc(PCI_NIRQ, 8);
for (i = 0; i < PCI_NIRQ; i++) {
alpha_shared_intr_set_maxstrays(dec_1000a_pci_intr, i,
PCI_STRAY_MAX);
cp = alpha_shared_intr_string(dec_1000a_pci_intr, i);
sprintf(cp, "irq %d", i);
evcnt_attach_dynamic(alpha_shared_intr_evcnt(
dec_1000a_pci_intr, i), EVCNT_TYPE_INTR, NULL,
"dec_1000a", cp);
}
pci_1000a_imi();
#if NSIO > 0 || NPCEB > 0
sio_intr_setup(pc, iot);
#endif
}
void
sio_intr_setup(pci_chipset_tag_t pc, bus_space_tag_t iot)
{
char *cp;
int i;
sio_iot = iot;
sio_pc = pc;
if (bus_space_map(sio_iot, IO_ICU1, 2, 0, &sio_ioh_icu1) ||
bus_space_map(sio_iot, IO_ICU2, 2, 0, &sio_ioh_icu2))
panic("sio_intr_setup: can't map ICU I/O ports");
for (i = 0; sio_elcr_setup_funcs[i] != NULL; i++)
if ((*sio_elcr_setup_funcs[i])() == 0)
break;
if (sio_elcr_setup_funcs[i] == NULL)
panic("sio_intr_setup: can't map ELCR");
#ifdef BROKEN_PROM_CONSOLE
/*
* Remember the initial values, so we can restore them later.
*/
initial_ocw1[0] = bus_space_read_1(sio_iot, sio_ioh_icu1, 1);
initial_ocw1[1] = bus_space_read_1(sio_iot, sio_ioh_icu2, 1);
initial_elcr[0] = (*sio_read_elcr)(0); /* XXX */
initial_elcr[1] = (*sio_read_elcr)(1); /* XXX */
shutdownhook_establish(sio_intr_shutdown, 0);
#endif
#define PCI_SIO_IRQ_STR 8
sio_intr = alpha_shared_intr_alloc(ICU_LEN, PCI_SIO_IRQ_STR);
/*
* set up initial values for interrupt enables.
*/
for (i = 0; i < ICU_LEN; i++) {
alpha_shared_intr_set_maxstrays(sio_intr, i, STRAY_MAX);
cp = alpha_shared_intr_string(sio_intr, i);
snprintf(cp, PCI_SIO_IRQ_STR, "irq %d", i);
evcnt_attach_dynamic(alpha_shared_intr_evcnt(sio_intr, i),
EVCNT_TYPE_INTR, NULL, "isa", cp);
switch (i) {
case 0:
case 1:
case 8:
case 13:
/*
* IRQs 0, 1, 8, and 13 must always be
* edge-triggered.
*/
sio_setirqstat(i, 0, IST_EDGE);
alpha_shared_intr_set_dfltsharetype(sio_intr, i,
IST_EDGE);
specific_eoi(i);
break;
case 2:
/*
* IRQ 2 must be edge-triggered, and should be
* enabled (otherwise IRQs 8-15 are ignored).
*/
sio_setirqstat(i, 1, IST_EDGE);
alpha_shared_intr_set_dfltsharetype(sio_intr, i,
IST_UNUSABLE);
break;
default:
/*
* Otherwise, disable the IRQ and set its
* type to (effectively) "unknown."
*/
sio_setirqstat(i, 0, IST_NONE);
alpha_shared_intr_set_dfltsharetype(sio_intr, i,
IST_NONE);
specific_eoi(i);
break;
}
}
}
