void rx_ethernet_isr1 (void *context)
{
struct netif * netif = &TSE1netif;
//Poczekanie na zakoñczenie odbióru ramki ethernetowej z³¹czem po³¹czonym z eth_tse1
while (alt_avalon_sgdma_check_descriptor_status(&rx_descriptor1) != 0)
;
//dl odebranej ramki
pklen = IORD_16DIRECT(&(rx_descriptor1.actual_bytes_transferred),0);
//printf("dlugosc odebranych danych to: %d",pklen);
memcpy(tx_frame,rx_frame1,pklen);
p->payload=tx_frame;
ethernet_input(p,netif);
alt_avalon_sgdma_construct_mem_to_stream_desc( &tx_descriptor, &tx_descriptor_end, (alt_u32 *)tx_frame, pklen-4, 0, 1, 1, 0 );
alt_avalon_sgdma_do_async_transfer( sgdma_tx_dev, &tx_descriptor );
while (alt_avalon_sgdma_check_descriptor_status(&tx_descriptor) != 0);
alt_avalon_sgdma_construct_stream_to_mem_desc( &rx_descriptor1, &rx_descriptor_end1, (alt_u32 *)rx_frame1, 0, 0 );
alt_avalon_sgdma_do_async_transfer( sgdma_rx_dev1, &rx_descriptor1 );
p->len=0;
p->tot_len=0;
}
void rx_ethernet_isr (void *context)
{
struct netif * netif = &TSE1netif;
//Poczekanie na zakoñczenie odbioru ramki ethernetowej z³¹czem po³¹czonym z eth_tse
while (alt_avalon_sgdma_check_descriptor_status(&rx_descriptor) != 0)
;
//zapisanie do zmiennej pklen dlugosci odebranej ramki ethernetowej
pklen = IORD_16DIRECT(&(rx_descriptor.actual_bytes_transferred),0);
memcpy(tx_frame,rx_frame,pklen);
p->payload=tx_frame;
// funkcja lwip ethernet_input obslugujaca ramkê Ethernetow¹
ethernet_input(p,netif);
//Wys³anie ramki ethernetowej z³¹czem po³¹czonym z eth_tse1
alt_avalon_sgdma_construct_mem_to_stream_desc( &tx_descriptor1,
&tx_descriptor_end1, (alt_u32 *)tx_frame, pklen-4, 0, 1, 1, 0 );
alt_avalon_sgdma_do_async_transfer( sgdma_tx_dev1, &tx_descriptor1 );
while (alt_avalon_sgdma_check_descriptor_status(&tx_descriptor1) != 0);
//Ponowne skonsturowanie deskryptorów odbiorczych z³¹cza eth_tse
alt_avalon_sgdma_construct_stream_to_mem_desc( &rx_descriptor,
&rx_descriptor_end, (alt_u32 *)rx_frame, 0, 0 );
alt_avalon_sgdma_do_async_transfer( sgdma_rx_dev, &rx_descriptor );
//wyzerowanie pól z d³ugociami bufora lwIP
p->len=0;
p->tot_len=0;
}
/**
* Funkcja realizujaca deszyfrowanie z uzyciem modulu potokowej wersji Triple DES
*/
void deciph_3des_pot ( unsigned char *data, unsigned char *deciph_data, unsigned int length)
{
//przes³anie do zdeszyfrowania:
alt_avalon_sgdma_construct_mem_to_stream_desc( &tdesdecryptin_descriptor,
&tdesdecryptin_descriptor_end, (alt_u32 *)data, length, 0, 1, 1, 0 );
while(alt_avalon_sgdma_do_async_transfer( sgdma_in_decrypt_dev, &tdesdecryptin_descriptor ) != 0) ;
//zapis do pamieci zdeszyfrowanych danych:
alt_avalon_sgdma_construct_stream_to_mem_desc( &tdesdecryptout_descriptor,
&tdesdecryptout_descriptor_end, (alt_u32 *) deciph_data, 0, 0 );
while(alt_avalon_sgdma_do_async_transfer( sgdma_out_decrypt_dev, &tdesdecryptout_descriptor ) != 0) ;
}
/**
* Funkcja realizujaca szyfrowanie z uzyciem modulu potokowej wersji Triple DES
*/
void ciph_3des_pot ( unsigned char *data, unsigned char *ciph_data, unsigned int length)
{
//przes³anie danych do zaszyfrowania:
alt_avalon_sgdma_construct_mem_to_stream_desc( &tdesin_descriptor,
&tdesin_descriptor_end, (alt_u32 *)data, length, 0, 1, 1, 0 );
while(alt_avalon_sgdma_do_async_transfer( sgdma_in_dev, &tdesin_descriptor ) != 0)
{ printf("Zapis do szyfratora 3DES sie nie powiodl\n"); }
//zapis do pamieci zaszyfrowanych danych:
alt_avalon_sgdma_construct_stream_to_mem_desc( &tdesout_descriptor,
&tdesout_descriptor_end, (alt_u32 *)ciph_data, 0, 0 );
while((alt_avalon_sgdma_do_async_transfer( sgdma_out_dev, &tdesout_descriptor ) != 0));
}
int main(int argc, char **argv) {
char c;
int uart_fd = open("/dev/uart", O_RDWR);
if (uart_fd == NULL) {
printf("Error opening uart\n");
return 1;
}
alt_sgdma_dev *transmit_dma = alt_avalon_sgdma_open("/dev/sgdma_0");
receive_dma = alt_avalon_sgdma_open("/dev/sgdma_1");
alt_sgdma_descriptor *transmit_descriptors[2],
*transmit_descriptors_copy[2];
// alt_sgdma_descriptor *receive_descriptors[2], *receive_descriptors_copy[2];
alt_u32 *transmit_ptr, *receive_ptr;
if (transmit_dma == NULL) {
printf("Could not open transmit SG-DMA");
return 1;
}
if (receive_dma == NULL) {
printf("Could not open the receive SG-DMA\n");
return 1;
}
alt_u32 return_code = descriptor_allocation(&transmit_descriptors[0],
&transmit_descriptors_copy[0], &receive_descriptors[0],
&receive_descriptors_copy[0],
NUMBER_OF_BUFFERS);
if (return_code == 1) {
printf("Allocating the descriptor memory failed... exiting\n");
return 1;
}
return_code = descriptor_allocation(&transmit_descriptors[1],
&transmit_descriptors_copy[1], &receive_descriptors[1],
&receive_descriptors_copy[1],
NUMBER_OF_BUFFERS);
if (return_code == 1) {
printf("Allocating the descriptor memory failed... exiting\n");
return 1;
}
printf("Transmit descriptor: 0x%08x\n", transmit_descriptors[0]);
printf("Receive descriptor: 0x%08x\n", receive_descriptors[0]);
alt_avalon_sgdma_register_callback(transmit_dma,
&transmit_callback_function,
(ALTERA_AVALON_SGDMA_CONTROL_IE_GLOBAL_MSK
| ALTERA_AVALON_SGDMA_CONTROL_IE_CHAIN_COMPLETED_MSK),
NULL);
alt_avalon_sgdma_register_callback(receive_dma, &receive_callback_function,
(ALTERA_AVALON_SGDMA_CONTROL_IE_GLOBAL_MSK
| ALTERA_AVALON_SGDMA_CONTROL_IE_CHAIN_COMPLETED_MSK),
NULL);
printf("Starting up the SGDMA engines\n");
alt_u32* transmit_ptrs[2][NUMBER_OF_BUFFERS];
int i, j;
for (j = 0; j < 2; j++) {
for (i = 0; i < NUMBER_OF_BUFFERS; i++) {
transmit_ptr = (alt_u32 *) malloc(MAXIMUM_BUFFER_LENGTH); // this descriptor will point at a buffer of length (temp_length)
if (transmit_ptr == NULL) {
printf("Allocating a transmit buffer region failed\n");
return 1;
}
transmit_ptrs[j][i] = transmit_ptr;
}
for (i = 0; i < NUMBER_OF_BUFFERS; i++) {
alt_avalon_sgdma_construct_mem_to_stream_desc(
&transmit_descriptors[j][i], // descriptor
&transmit_descriptors[j][i + 1], // next descriptor
transmit_ptrs[j][i], // read buffer location
(alt_u16) MAXIMUM_BUFFER_LENGTH, // length of the buffer
0, // reads are not from a fixed location
0, // start of packet is enabled for the Avalon-ST interfaces
0, // end of packet is enabled for the Avalon-ST interfaces,
0); // there is only one channel
}
}
// alt_u32* receive_ptrs[2][NUMBER_OF_BUFFERS];
for (j = 0; j < 2; j++) {
for (i = 0; i < NUMBER_OF_BUFFERS; i++) {
receive_ptr = (alt_u32 *) malloc(MAXIMUM_BUFFER_LENGTH); // this descriptor will point at a buffer of length (temp_length)
if (receive_ptr == NULL) {
printf("Allocating a receive buffer region failed\n");
return 1;
}
receive_ptrs[j][i] = receive_ptr;
}
for (i = 0; i < NUMBER_OF_BUFFERS; i++) {
alt_avalon_sgdma_construct_stream_to_mem_desc(
&receive_descriptors[j][i], // descriptor
&receive_descriptors[j][i + 1], // next descriptor
receive_ptrs[j][i], // read buffer location
(alt_u16) MAXIMUM_BUFFER_LENGTH, // length of the buffer
0); // there is only one channel
}
}
if (alt_avalon_sgdma_do_async_transfer(receive_dma,
&receive_descriptors[dbufr][0]) != 0) {
printf(
"Writing the head of the receive descriptor list to the DMA failed\n");
return 1;
}
int buffer_counter = 0;
int dbuft = 0;
int char_count = 0;
while (1) {
int num_read = readall(uart_fd, transmit_ptrs[dbuft][buffer_counter],
MAXIMUM_BUFFER_LENGTH);
if (num_read > 0) {
alt_avalon_sgdma_construct_mem_to_stream_desc(
&transmit_descriptors[dbuft][buffer_counter], // descriptor
&transmit_descriptors[dbuft][buffer_counter + 1], // next descriptor
transmit_ptrs[dbuft][buffer_counter], // read buffer location
(alt_u16) num_read, // length of the buffer
0, // reads are not from a fixed location
0, // start of packet is enabled for the Avalon-ST interfaces
0, // end of packet is enabled for the Avalon-ST interfaces,
0); // there is only one channel
buffer_counter++;
if (buffer_counter >= NUMBER_OF_BUFFERS) {
buffer_counter = 0;
dbuft++;
if (dbuft > 1) {
dbuft = 0;
}
if (tx_done) {
if (alt_avalon_sgdma_do_async_transfer(transmit_dma,
&transmit_descriptors[dbuft][0]) != 0) {
printf(
"Writing the head of the transmit descriptor list to the DMA failed\n");
return 1;
}
tx_done = 0;
}
}
}
/*
if ((IORD(UART_BASE,2) & 0x80)) {
c = IORD(UART_BASE, 0);
*transmit_ptr++ = c;
char_count++;
if (char_count >= MAXIMUM_BUFFER_LENGTH) {
char_count = 0;
transmit_ptr = transmit_ptrs[dbuft][buffer_counter];
alt_avalon_sgdma_construct_mem_to_stream_desc(
&transmit_descriptors[dbuft][buffer_counter], // descriptor
&transmit_descriptors[dbuft][buffer_counter + 1], // next descriptor
transmit_ptrs[dbuft][buffer_counter], // read buffer location
(alt_u16) MAXIMUM_BUFFER_LENGTH, // length of the buffer
0, // reads are not from a fixed location
0, // start of packet is enabled for the Avalon-ST interfaces
0, // end of packet is enabled for the Avalon-ST interfaces,
0); // there is only one channel
buffer_counter++;
if (buffer_counter >= NUMBER_OF_BUFFERS) {
buffer_counter = 0;
dbuft++;
if (dbuft > 1) {
dbuft = 0;
}
if (tx_done) {
if (alt_avalon_sgdma_do_async_transfer(transmit_dma,
&transmit_descriptors[dbuft][0]) != 0) {
printf(
"Writing the head of the transmit descriptor list to the DMA failed\n");
return 1;
}
tx_done = 0;
}
}
}
}
*/
if (rx_done) {
for (i = 0; i < NUMBER_OF_BUFFERS; i++) {
write(uart_fd, receive_ptrs[dbufr][i],
MAXIMUM_BUFFER_LENGTH);
}
rx_done = 0;
}
}
return 0;
}
/******************************************************************
* alt_video_display_setup_frame_descriptors
*
* Populate and prepare a video frame's SGDMA descriptors.
*
* Arguments:
* *display: The video display the frame is being prepared for
* *frame: The video frame you're constructing
* *buffer: The starting-address of your physical display buffer.
* This must be a single, continuous span of memory large enough
* for each pixel in the frame.
* *desc_base: The starting-address of memory allocated for
* SGDMA descriptors. Descriptor memory must be aligned to a
* 0x20 boundary.
******************************************************************/
void alt_video_display_setup_frame_descriptors(
alt_video_display *display,
alt_video_frame *frame,
alt_u32 *buffer,
alt_sgdma_descriptor *desc_base)
{
int i;
alt_u16 length;
alt_32 buffer_no_cache_bypass;
alt_sgdma_descriptor *last_descriptor;
/*
* We don't want the "uncached" bit set in the buffer address we hand
* off to the SGDMA, so we mask it out here.
*/
buffer_no_cache_bypass =
(alt_u32) alt_remap_cached( buffer, display->bytes_per_frame );
for(i=0; i<display->descriptors_per_frame; i++){
/*
* Calculate the data length associated with each descriptor, taking
* into account the edge cases
*/
if(i == (display->descriptors_per_frame-1)) {
length = (display->bytes_per_frame % ALT_VIDEO_DISPLAY_BYTES_PER_DESC);
/*
* The init routine calculated the number of desriptors per frame,
* based on frame size (bytes) and bytes per descriptor. Being evenly
* divisible on this last frame means a full-length sized frame.
*/
if(length == 0) {
length = ALT_VIDEO_DISPLAY_BYTES_PER_DESC;
}
}
else {
length = ALT_VIDEO_DISPLAY_BYTES_PER_DESC;
}
/* Construct the descriptor */
alt_avalon_sgdma_construct_mem_to_stream_desc(
(frame->desc_base + i), /* Descriptor */
( frame->desc_base + i + 1 ), /* Next descriptor */
(alt_u32*)( (alt_u8*)buffer_no_cache_bypass +
(ALT_VIDEO_DISPLAY_BYTES_PER_DESC*i) ), /* Read Address */
length, /* Transfer length */
0, /* Don't read fixed addr */
i==0?1:0, /* Generate SOP @ first desc */
i==(display->descriptors_per_frame-1)?1:0, /* Generate EOP @ last desc */
0 /* Streaming channel: N/A */
);
/*
* The last descriptor we created above requires a special modification:
* Its "next" pointer should point back to the first descriptor in the
* chain to create a loop.
*
* This was not done done in the above SGDMA descriptor creation routine
* call because that routine always terminates the 'next' descriptor
* pointer to prevent the SGDMA from continuing into unknown memory.
*/
if( i == ( display->descriptors_per_frame - 1 ) ) {
last_descriptor = (alt_sgdma_descriptor *) (frame->desc_base + i);
IOWR_32DIRECT((alt_u32)(&last_descriptor->next), 0,
(alt_u32)(frame->desc_base));
}
}
}
void rx_ethernet_isr (void *context)
{
int i;
// Wait until receive descriptor transfer is complete
while (alt_avalon_sgdma_check_descriptor_status(&rx_descriptor) != 0)
;
// Clear input line before writing
for (i = 0; i < (6 + text_length); i++) {
alt_printf( "%c", 0x08 ); // 0x1024008 --> backspace
}
// Output received text
// alt_printf( "receive> %s\n", rx_frame + 16 );
i=0;
// Set up non-blocking transfer of sgdma receive descriptor
int speed=alt_tse_mac_get_common_speed( ETH_TSE_BASE);
printf("Currents speed: %i",speed);
printf("\n");
//unsigned int *readtse;
//*readtse=
//volatile int * tse = (int *) ETH_TSE_BASE;
//*(tse + 0x3A)=0x00040000;
//printf("Readtse : %i",readtse);
printf("\n");
printf("odebrano ramke \n");
while(i<342)
{
alt_printf( "%x", rx_frame[i] );
i++;// 0x1024008 --> backspaces
if (rx_frame[i] =='\n')
{
i=1024;
}
}
// Reprint current input line after the outputs
// alt_printf( "send> %s", tx_frame + 16 );
i=0;
/*while (i<7)
{
tx_frame[i]=0x55;
i++;
}
tx_frame[7]=0xD5;*/
while (i<6)
{
tx_frame[i]=0xFF;
i++;
}
tx_frame[6]=0x01;
tx_frame[7]=0x60;
tx_frame[8]=0x6E;
tx_frame[9]=0x11;
tx_frame[10]=0x02;
tx_frame[11]=0x0F;
tx_frame[12]=0x08;
tx_frame[13]=0x00;
i=14;
while (i <88)
{
tx_frame[i]=rx_frame[i+1];
i++;
}
tx_frame[88]='\0';
alt_avalon_sgdma_construct_mem_to_stream_desc( &tx_descriptor, &tx_descriptor_end, (alt_u32 *)tx_frame, 92, 0, 1, 1, 0 );
alt_avalon_sgdma_do_async_transfer( sgdma_tx_dev, &tx_descriptor );
while (alt_avalon_sgdma_check_descriptor_status(&tx_descriptor) != 0);
//ff_tx_eop=1;
alt_avalon_sgdma_construct_stream_to_mem_desc( &rx_descriptor, &rx_descriptor_end, (alt_u32 *)rx_frame, 0, 0 );
alt_avalon_sgdma_do_async_transfer( sgdma_rx_dev, &rx_descriptor );
//alt_avalon_sgdma_do_async_transfer( sgdma_rx_dev, &rx_descriptor );
printf("\n");
printf("zakonczono odbior ramki\n");
// Create new receive sgdma descriptor
// alt_avalon_sgdma_construct_stream_to_mem_desc( &rx_descriptor, &rx_descriptor_end, (alt_u32 *)rx_frame, 0, 0 );
}
