static void init_dma0() { /* initialize interrupt context */ if ((dma_context->txchan = alt_dma_txchan_open("/dev/dma_0")) == NULL) { printf ("Failed to open transmit channel\n"); exit (1); } if ((dma_context->rxchan = alt_dma_rxchan_open("/dev/dma_0")) == NULL) { printf ("Failed to open receive channel\n"); exit (1); } dma_context->src = DMA_0_READ_MASTER_SRC_ON_CHIP_BASE; dma_context->dst = DMA_0_WRITE_MASTER_DST_ON_CHIP_BASE; //dma_context->len = (1 << (DMA_0_LENGTHWIDTH - 1)) - 1; // 32KB dma_context->len = 32; // 32KB dma_context->dma_done = 0; dma_context->done_callback = dma_done_func; /* Halt any current transactions (reset the device) */ //IOWR_ALTERA_AVALON_DMA_CONTROL (DMA_0_BASE, ALTERA_AVALON_DMA_CONTROL_SOFTWARERESET_MSK); IOWR_ALTERA_AVALON_DMA_CONTROL (DMA_0_BASE, ALTERA_AVALON_DMA_CONTROL_SOFTWARERESET_MSK); /* Set the default mode of the device (32 bit block reads and writes from/to memory). */ IOWR_ALTERA_AVALON_DMA_CONTROL (DMA_0_BASE, ALTERA_AVALON_DMA_CONTROL_WORD_MSK | ALTERA_AVALON_DMA_CONTROL_GO_MSK | ALTERA_AVALON_DMA_CONTROL_I_EN_MSK | ALTERA_AVALON_DMA_CONTROL_REEN_MSK | ALTERA_AVALON_DMA_CONTROL_WEEN_MSK | ALTERA_AVALON_DMA_CONTROL_LEEN_MSK); /* Clear any pending interrupts and the DONE flag */ IOWR_ALTERA_AVALON_DMA_STATUS (DMA_0_BASE, 0); /* kick off the transfer */ if(alt_dma_txchan_send(dma_context->txchan, (void *)dma_context->src, dma_context->len, NULL, NULL) < 0) printf("dma tx channel open error\n"); if(alt_dma_rxchan_prepare(dma_context->rxchan, (void *)dma_context->dst, dma_context->len, dma_context->done_callback, NULL) < 0) printf("dma rx channel open error\n"); /* Register the ISR. */ alt_ic_isr_register(DMA_0_IRQ_INTERRUPT_CONTROLLER_ID, DMA_0_IRQ, handle_dma0_interrupt, (void*)dma_context, 0x0); }
static void handle_dma0_interrupt(void* context) { alt_irq_context cpu_sr; dma_context_state *dma_context_int = (dma_context_state *)context; dma_context_int->dma_done = 0; // relaunch dma transfer alt_dma_txchan_send(dma_context_int->txchan, (void *)dma_context_int->src, dma_context_int->len, NULL, NULL); alt_dma_rxchan_prepare(dma_context_int->rxchan, (void *)dma_context_int->dst, dma_context_int->len, dma_context_int->done_callback, NULL); cpu_sr = alt_irq_disable_all(); alt_irq_enable_all(cpu_sr); OSSemPost(SEM_DMA0); }
int main() { int class; //da trasformate in alt_u8 o 16 in base alle dimensioni int vote; int end_class; alt_u16 command[256]; alt_u16 ack_cmd[3]; alt_u32 tr_size; alt_u32 tr_size_count; alt_u8 q_size; alt_u32 n_packet; alt_u32 tr_val; alt_u64 addr; //verificare dimensione alt_u64 q_addr; alt_u32 q_val; alt_u32 i = 0; alt_u32 k = 0; alt_u8 k_val; alt_u16 n_dim; alt_u16 n_load; alt_u16 n_load_count; alt_u16 n_cell; alt_u16 n_cell_last; alt_u64 count = 0; alt_u16 cache_q_addr = 0; alt_dma_txchan txchan; alt_dma_rxchan rxchan; alt_u32 memptr = 0; alt_u8 empty0 = 0; alt_u8 empty1 = 0; alt_u8 overflow = 0; unsigned char ledvalue = 1; void* tx_data; /* pointer to data to send */ void* rx_buffer; /* pointer to rx buffer */ while(1) { command[0] = 0; recv_short(command, 8); //send back the ACK ack_cmd[0] = ACK; ack_cmd[1] = ACK; ack_cmd[2] = command[3]; send_short(ack_cmd, 3); if(command[0] == FLUSH_COMM) { tr_size = 0; tr_size = command[1]; tr_size = tr_size<<16; tr_size = tr_size | command[2]; n_packet = 0; n_packet = command[3]; n_packet = n_packet<<16; n_packet = n_packet | command[4]; cache_q_addr = command[5]; addr = 0; tr_size_count = 0; for(i = 0; i < n_packet;i++) { recv_short(command, 256); send_short(command, 256); for(k = 0;k < 127; k++) { if(tr_size_count < tr_size) { tr_size_count = tr_size_count + 1; tr_val = 0; tr_val = command[2+2*k]; tr_val = tr_val<<16; tr_val = tr_val | command[3+2*k]; IOWR_32DIRECT(SDRAM_CONTROLLER_BASE,addr,tr_val); addr = addr + 0x04; } } } ack_cmd[0] = ACK; ack_cmd[1] = ACK; ack_cmd[2] = command[3]; send_short(ack_cmd, 3); } else if(command[0] == CLASS_CMD) { q_size = 0; q_size = command[1]; q_size = q_size<<16; q_size = q_size | command[2]; n_dim = 0; n_dim = command[3]; k_val = 0; k_val = command[4]; n_load = 0; n_load = command[5]; n_cell = 0; n_cell = command[6]; n_cell_last = 0; n_cell_last = command[7]; for(i = 0; i < 1;i++) { recv_short(command, 256); send_short(command, 256); } q_addr = SDRAM_Q_ADDR_BASE; for(i = 0;i < q_size; i++) { q_val = 0; q_val = command[2*i]; q_val = q_val<<16; q_val = q_val | command[1+2*i]; IOWR_32DIRECT(SDRAM_CONTROLLER_BASE, q_addr, q_val); q_addr = q_addr + 0x04; } // set the number of dimension MAX = 256 IOWR_32DIRECT(KNNCLASSCORE_BASE, STARTCLREG,0x00000000); IOWR_32DIRECT(BASEQADDR_0_BASE,0x00,cache_q_addr); IOWR_32DIRECT(SKIPADDRREG_0_BASE,0x00,(q_size+1)*4); IOWR_32DIRECT(NDIMREG_BASE,0x00,n_dim); // number of training val in each mem IOWR_32DIRECT(NTRREG_0_BASE,0x00,3); IOWR_32DIRECT(NTRREG_1_BASE,0x00,3); // k val IOWR_32DIRECT(KNNCLASSCORE_BASE,KVALREG,k_val); IOWR_32DIRECT(ENDTSETREG_0_BASE,0x00,0); IOWR_32DIRECT(ENDTSETREG_1_BASE,0x00,0); load_q_cache1 = 0; load_q_cache0 = 0; IOWR_32DIRECT(FULLREG_0_BASE,0x00,0x00000000); IOWR_32DIRECT(FULLREG_1_BASE,0x00,0x00000000); PERF_RESET(PERFORMANCE_COUNTER_0_BASE); PERF_START_MEASURING(PERFORMANCE_COUNTER_0_BASE); PERF_BEGIN(PERFORMANCE_COUNTER_0_BASE,1); IOWR_32DIRECT(KNNCLASSCORE_BASE, STARTCLREG,0x00000001); txchan = alt_dma_txchan_open("/dev/dma"); rxchan = alt_dma_rxchan_open("/dev/dma"); alt_dma_txchan_ioctl(txchan, ALT_DMA_SET_MODE_32, NULL); alt_dma_rxchan_ioctl(rxchan, ALT_DMA_SET_MODE_32, NULL); txrx_doneCache0 = 0; tx_data = (void*)(SDRAM_CONTROLLER_BASE+SDRAM_Q_ADDR_BASE); /* pointer to data to send */ rx_buffer = (void*)(DMA_WRITE_MASTER_CACHE_0_BASE+cache_q_addr);//CUSTOM_RAM_0_BASE alt_dma_txchan_send (txchan,tx_data,q_size*4,NULL,NULL); alt_dma_rxchan_prepare (rxchan,rx_buffer,q_size*4, txrxDoneCache0,NULL); alt_dma_txchan_ioctl(txchan, ALT_DMA_SET_MODE_32, NULL); alt_dma_rxchan_ioctl(rxchan, ALT_DMA_SET_MODE_32, NULL); txrx_doneCache1 = 0; tx_data = (void*)(SDRAM_CONTROLLER_BASE+SDRAM_Q_ADDR_BASE); /* pointer to data to send */ rx_buffer = (void*)(DMA_WRITE_MASTER_CACHE_1_BASE+cache_q_addr);//CUSTOM_RAM_0_BASE alt_dma_txchan_send (txchan,tx_data,q_size*4,NULL,NULL); alt_dma_rxchan_prepare (rxchan,rx_buffer,q_size*4, txrxDoneCache1,NULL); IOWR_ALTERA_AVALON_PIO_DATA(PIO_0_BASE, ledvalue); ledvalue++; n_load_count = 0; memptr = 0; IOWR_32DIRECT(KNNCLASSCORE_BASE,STARTCLREG,1); //modificato qui //fill cache 0 empty0 = IORD_32DIRECT(EMPTYREG_0_BASE,0x00); empty1 = IORD_32DIRECT(EMPTYREG_1_BASE,0x00); while(txrx_doneCache1==0 || txrx_doneCache1==0); while(n_load_count < n_load) { if(empty0 && (n_load_count < n_load) && txrx_doneCache0 ) // && !endmem0 { IOWR_32DIRECT(FULLREG_0_BASE,0x00,0x00000000); IOWR_32DIRECT(ENDTSETREG_0_BASE,0x00,0); if(n_load_count == n_load-1) IOWR_32DIRECT(NTRREG_0_BASE, 0x00,n_cell_last/(4*(q_size+1))); else IOWR_32DIRECT(NTRREG_0_BASE, 0x00,n_cell/(4*(q_size+1))); txrx_doneCache0 = 0; alt_dma_txchan_ioctl(txchan, ALT_DMA_SET_MODE_32, NULL); alt_dma_rxchan_ioctl(rxchan, ALT_DMA_SET_MODE_32, NULL); tx_data = (void*)(SDRAM_CONTROLLER_BASE+memptr); /* pointer to data to send */ rx_buffer = (void*)(DMA_WRITE_MASTER_CACHE_0_BASE);//CUSTOM_RAM_0_BASE if(n_load_count == n_load-1) { alt_dma_txchan_send (txchan,tx_data,n_cell_last,NULL,NULL); alt_dma_rxchan_prepare (rxchan,rx_buffer,n_cell_last, txrxDoneCache0,NULL); } else { alt_dma_txchan_send (txchan,tx_data,n_cell,NULL,NULL); alt_dma_rxchan_prepare (rxchan,rx_buffer,n_cell, txrxDoneCache0,NULL); } memptr = memptr + n_cell; n_load_count++; IOWR_32DIRECT(FULLREG_0_BASE,0x00,0x00000001); } if(empty1 && (n_load_count< n_load) && txrx_doneCache1) // && !endmem0 { //fill cache 1 IOWR_32DIRECT(FULLREG_1_BASE,0x00,0x00000000); IOWR_32DIRECT(ENDTSETREG_1_BASE,0x00,0); //era 1 if(n_load_count == n_load-1) IOWR_32DIRECT(NTRREG_1_BASE, 0x00,n_cell_last/(4*(q_size+1))); else IOWR_32DIRECT(NTRREG_1_BASE, 0x00,n_cell/(4*(q_size+1))); alt_dma_txchan_ioctl(txchan, ALT_DMA_SET_MODE_32, NULL); alt_dma_rxchan_ioctl(rxchan, ALT_DMA_SET_MODE_32, NULL); txrx_doneCache1 = 0; tx_data = (void*)(SDRAM_CONTROLLER_BASE+memptr); /* pointer to data to send */ rx_buffer = (void*)(DMA_WRITE_MASTER_CACHE_1_BASE);//CUSTOM_RAM_0_BASE if(n_load_count == n_load-1) { alt_dma_txchan_send (txchan,tx_data,n_cell_last,NULL,NULL); alt_dma_rxchan_prepare (rxchan,rx_buffer,n_cell_last, txrxDoneCache1,NULL); } else { alt_dma_txchan_send (txchan,tx_data,n_cell,NULL,NULL); alt_dma_rxchan_prepare (rxchan,rx_buffer,n_cell, txrxDoneCache1,NULL); } memptr = memptr + n_cell; n_load_count++; IOWR_32DIRECT(FULLREG_1_BASE,0x00,0x00000001); } empty0 = IORD_32DIRECT(EMPTYREG_0_BASE,0x00); empty1 = IORD_32DIRECT(EMPTYREG_1_BASE,0x00); } while(txrx_doneCache1==0 || txrx_doneCache1==0); //while(empty0==0 || empty1==0); IOWR_32DIRECT(ENDTSETREG_0_BASE,0x00,1); //era 1 IOWR_32DIRECT(ENDTSETREG_1_BASE,0x00,1); //era 1 end_class = 0; while (!end_class) end_class = IORD_32DIRECT(KNNCLASSCORE_BASE,ENDCLASSREG); alt_dma_txchan_close(txchan); alt_dma_rxchan_close(rxchan); PERF_END(PERFORMANCE_COUNTER_0_BASE,1); class = IORD_32DIRECT(KNNCLASSCORE_BASE,CLREG); vote = IORD_32DIRECT(KNNCLASSCORE_BASE,NVOTREG); count = perf_get_section_time(PERFORMANCE_COUNTER_0_BASE,1); overflow = IORD_32DIRECT(KNNCLASSCORE_BASE,OVERFLOWREG); command[0] = class; command[1] = vote; command[2] = count; count = count>>16; command[3] = count; count = count>>16; command[4] = count; count = count>>16; command[5] = count; command[6] = overflow; addr = 0; for(i=0; i < 16; i++) { command[7+i] = IORD_32DIRECT(KNNCLASSCORE_BASE,addr); addr = addr + 0x04; } send_short(command, 23); } }
static int MemDMATest(unsigned int memory_base, unsigned int nBytes) { int rc; int ret_code = 0; int pattern, offset; alt_dma_txchan txchan; alt_dma_rxchan rxchan; void* data_written; void* data_read; /* Get a couple buffers for the test */ data_written = (void*)alt_uncached_malloc(0x1000); data_read = (void*)alt_uncached_malloc(0x1000); /* Fill write buffer with known values */ for (pattern = 1, offset = 0; offset < sizeof(data_written); pattern++, offset+=4) { IOWR_32DIRECT((int)data_written, offset, pattern); } /* Create the transmit channel */ if ((txchan = alt_dma_txchan_open("/dev/dma")) == NULL) { printf ("Failed to open transmit channel\n"); exit (1); } /* Create the receive channel */ if ((rxchan = alt_dma_rxchan_open("/dev/dma")) == NULL) { printf ("Failed to open receive channel\n"); exit (1); } for(offset = memory_base; offset < (memory_base + nBytes); offset += 0x1000) { /* Use DMA to transfer from write buffer to memory under test */ /* Post the transmit request */ if ((rc = alt_dma_txchan_send (txchan, data_written, 0x1000, NULL, NULL)) < 0) { printf ("Failed to post transmit request, reason = %i\n", rc); exit (1); } /* Post the receive request */ if ((rc = alt_dma_rxchan_prepare (rxchan, (void*)offset, 0x1000, dma_done, NULL)) < 0) { printf ("Failed to post read request, reason = %i\n", rc); exit (1); } /* Wait for transfer to complete */ while (!rx_done); rx_done = 0; /* Clear the read buffer before we fill it */ memset(data_read, 0, 0x1000); /* Use DMA to read data back into read buffer from memory under test */ /* Post the transmit request */ if ((rc = alt_dma_txchan_send (txchan, (void*)offset, 0x1000, NULL, NULL)) < 0) { printf ("Failed to post transmit request, reason = %i\n", rc); exit (1); } /* Post the receive request */ if ((rc = alt_dma_rxchan_prepare (rxchan, data_read, 0x1000, dma_done, NULL)) < 0) { printf ("Failed to post read request, reason = %i\n", rc); exit (1); } /* Wait for transfer to complete */ while (!rx_done); rx_done = 0; if (memcmp(data_written, data_read, 0x1000)) { ret_code = offset; break; } } alt_uncached_free(data_written); alt_uncached_free(data_read); return ret_code; }
int main() { printf("hello\n"); unsigned volatile long int j; unsigned short i; int k; int rc; void* tx_data = RAM1_BASE; void* rx_buffer = SDRAM_BASE; for(i=0;i<640;i++){ IOWR_16DIRECT(RAM1_BASE,i*2,i); } alt_dma_txchan txchan; alt_dma_rxchan rxchan; if ((txchan = alt_dma_txchan_open("/dev/DMA")) == NULL) { return 0; } if ((rxchan = alt_dma_rxchan_open("/dev/DMA")) == NULL) { return 0; } alt_dma_rxchan_ioctl(rxchan,ALT_DMA_SET_MODE_16,done); alt_dma_txchan_ioctl(txchan,ALT_DMA_SET_MODE_16,done); IOWR_16DIRECT(LED_BASE,0,0x1); if ((rc = alt_dma_txchan_send (txchan, tx_data, 640*2, NULL, NULL)) < 0) { return 0; } for(k=0;k<480;k++){ if ((rc = alt_dma_rxchan_prepare (rxchan, rx_buffer+k*1280, 640*2, done, NULL)) < 0) { exit (1); } while (!rx_done); IOWR_16DIRECT(LED_BASE,0,0x3); } while(1) { } return 0; }
int main() { printf("hello\n"); int j=0; int i=0; int rc; void* tx_data = AVALON_MM_CAMERA_CONTROLLER_BASE+2; void* rx_buffer = SDRAM_BASE; alt_dma_txchan txchan; alt_dma_rxchan rxchan; if ((txchan = alt_dma_txchan_open("/dev/dma")) == NULL) { return 0; } if ((rxchan = alt_dma_rxchan_open("/dev/dma")) == NULL) { return 0; } alt_dma_rxchan_ioctl(rxchan,ALT_DMA_SET_MODE_16,done); alt_dma_txchan_ioctl(txchan,ALT_DMA_SET_MODE_16,done); i=1; while(i < 5){ while(!(IORD_16DIRECT(AVALON_MM_CAMERA_CONTROLLER_BASE,1282*2) == (0x400 + i))){ IOWR_16DIRECT(AVALON_MM_CAMERA_CONTROLLER_BASE,1281*2,0x1); } if(i%2 == 0){ if ((rc = alt_dma_txchan_send (txchan, tx_data, 640 * 2, NULL, NULL)) < 0) { return 0; } }else{ if ((rc = alt_dma_txchan_send (txchan, tx_data + 1280, 640 * 2, NULL, NULL)) < 0) { return 0; } } if ((rc = alt_dma_rxchan_prepare (rxchan, rx_buffer + 1280*(i-1), 640*2, done, NULL)) < 0) { return 0; } while (!rx_done); i++; } while (1); return 0; }