/** * am33xx_cm_module_disable - Disable the module inside CLKCTRL * @part: CM partition, ignored for AM33xx * @inst: CM instance register offset (*_INST macro) * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro) * * No return value. */ static void am33xx_cm_module_disable(u8 part, u16 inst, u16 clkctrl_offs) { u32 v; v = am33xx_cm_read_reg(inst, clkctrl_offs); v &= ~AM33XX_MODULEMODE_MASK; am33xx_cm_write_reg(v, inst, clkctrl_offs); }
/** * am33xx_cm_module_enable - Enable the modulemode inside CLKCTRL * @mode: Module mode (SW or HW) * @inst: CM instance register offset (*_INST macro) * @cdoffs: Clockdomain register offset (*_CDOFFS macro) * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro) * * No return value. */ void am33xx_cm_module_enable(u8 mode, u16 inst, s16 cdoffs, u16 clkctrl_offs) { u32 v; v = am33xx_cm_read_reg(inst, clkctrl_offs); v &= ~AM33XX_MODULEMODE_MASK; v |= mode << AM33XX_MODULEMODE_SHIFT; am33xx_cm_write_reg(v, inst, clkctrl_offs); }
/** * _clktrctrl_write - write @c to a CM_CLKSTCTRL.CLKTRCTRL register bitfield * @c: CLKTRCTRL register bitfield (LSB = bit 0, i.e., unshifted) * @inst: CM instance register offset (*_INST macro) * @cdoffs: Clockdomain register offset (*_CDOFFS macro) * * @c must be the unshifted value for CLKTRCTRL - i.e., this function * will handle the shift itself. */ static void _clktrctrl_write(u8 c, u16 inst, u16 cdoffs) { u32 v; v = am33xx_cm_read_reg(inst, cdoffs); v &= ~AM33XX_CLKTRCTRL_MASK; v |= c << AM33XX_CLKTRCTRL_SHIFT; am33xx_cm_write_reg(v, inst, cdoffs); }
/* Read-modify-write a register in CM */ static inline u32 am33xx_cm_rmw_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx) { u32 v; v = am33xx_cm_read_reg(inst, idx); v &= ~mask; v |= bits; am33xx_cm_write_reg(v, inst, idx); return v; }