static void aucodec_digitalio_on_1(void)
{
/* aucodec_digitalio_on */
#if (CHIP_REV == A3)||(CHIP_REV == A5)||(CHIP_REV == A6)|| \
(CHIP_REV == A5S)||(CHIP_REV == I1)||(CHIP_REV == S2)
unsigned long flags;
ambarella_gpio_raw_lock(1, &flags);
amba_clrbitsl(GPIO1_AFSEL_REG, 0x80000000);
ambarella_gpio_raw_unlock(1, &flags);
/* GPIO77~GPIO78 and GPIO81~GPIO83 program as hardware mode */
ambarella_gpio_raw_lock(2, &flags);
amba_setbitsl(GPIO2_AFSEL_REG, 0x000e6000);
ambarella_gpio_raw_unlock(2, &flags);
#elif (CHIP_REV == S2)
unsigned long flags;
ambarella_gpio_raw_lock(3, &flags);
amba_clrbitsl(GPIO3_AFSEL_REG, 0x0000000c);
ambarella_gpio_raw_unlock(3, &flags);
/* GPIO82~GPIO83 program as hardware mode */
ambarella_gpio_raw_lock(2, &flags);
amba_setbitsl(GPIO2_AFSEL_REG, 0x000c0000);
ambarella_gpio_raw_unlock(2, &flags);
#else
pr_err("aucodec_digitalio_on: Unknown Chip Architecture\n");
#endif
}
int __init ambarella_init_fio(void)
{
#ifndef CONFIG_AMBARELLA_QUICK_INIT
/* Following should be handled by the bootloader... */
#if (HOST_MAX_AHB_CLK_EN_BITS == 10)
amba_clrbitsl(HOST_AHB_CLK_ENABLE_REG,
(HOST_AHB_BOOT_SEL | HOST_AHB_FDMA_BURST_DIS));
#endif
rct_reset_fio();
fio_amb_exit_random_mode();
enable_fio_dma();
amba_writel(FLASH_INT_REG, 0x0);
amba_writel(XD_INT_REG, 0x0);
amba_writel(CF_STA_REG, CF_STA_CW | CF_STA_DW);
#endif
//SMIO_38 ~ SMIO_43
amba_setbitsl(GPIO2_MASK_REG, 0x000007e0);
amba_clrbitsl(GPIO2_DIR_REG, 0x00000780);
amba_setbitsl(GPIO2_DIR_REG, 0x00000060);
amba_setbitsl(GPIO2_DATA_REG, 0x00000040);
amba_clrbitsl(GPIO2_DATA_REG, 0x00000020);
return 0;
}
void ambarella_disable_usb_port(int owner)
{
#if defined(CONFIG_PLAT_AMBARELLA_SUPPORT_HAL)
#if (CHIP_REV == A5S) || (CHIP_REV == A7)
if (amb_set_usb_interface_state(HAL_BASE_VP, AMB_USB_OFF)
!= AMB_HAL_SUCCESS) {
pr_info("%s: amb_set_usb_interface_state fail!\n", __func__);
}
#elif (CHIP_REV == I1)
if (amb_set_usb_port0_state(HAL_BASE_VP, AMB_USB_OFF)
!= AMB_HAL_SUCCESS) {
pr_info("%s: amb_set_usb_port0_state fail!\n", __func__);
}
/* We disable usb port1 when neither UHC nor UDC use it */
ambarella_usb_port_owner &= (~owner);
if (ambarella_usb_port_owner == 0) {
if (amb_set_usb_port1_state(HAL_BASE_VP, AMB_USB_OFF)
!= AMB_HAL_SUCCESS) {
pr_info("%s: amb_set_usb_port1_state fail!\n", __func__);
}
}
#elif (CHIP_REV == S2)
/* We disable usb port when neither UHC nor UDC use it */
ambarella_usb_port_owner &= (~owner);
if (ambarella_usb_port_owner == 0)
amb_set_usb_port_state(HAL_BASE_VP, AMB_USB_OFF);
#elif (CHIP_REV == A7L)
if (amb_set_usb_port1_state(HAL_BASE_VP, AMB_USB_OFF)
!= AMB_HAL_SUCCESS) {
pr_info("%s: amb_set_usb_port1_state fail!\n", __func__);
}
#endif
#else
#if (CHIP_REV == A5S) || (CHIP_REV == A7) || (CHIP_REV == A7L)
amba_clrbitsl(ANA_PWR_REG, 0x6);
#elif (CHIP_REV == I1)
amba_clrbitsl(ANA_PWR_REG, 0x3000);
/* We disable usb port when neither UHC nor UDC use it */
ambarella_usb_port_owner &= (~owner);
if (ambarella_usb_port_owner == 0)
amba_clrbitsl(ANA_PWR_REG, 0x6);
#elif (CHIP_REV == S2)
/* We disable usb port when neither UHC nor UDC use it */
ambarella_usb_port_owner &= (~owner);
if (ambarella_usb_port_owner == 0)
amba_clrbitsl(ANA_PWR_REG, 0x6);
#endif
#endif
}
static inline void ambarella_ce_timer_disable(void)
{
#if !defined(CONFIG_MACH_HYACINTH_0) && !defined(CONFIG_MACH_HYACINTH_1)
amba_clrbitsl(TIMER_CTR_REG, AMBARELLA_CE_TIMER_CTR_EN);
#else /* defined(CONFIG_MACH_HYACINTH_0) || defined(CONFIG_MACH_HYACINTH_1) */
if (machine_is_hyacinth_0())
amba_clrbitsl(TIMER_CTR_REG, AMBARELLA_CE_TIMER_AXI0_CTR_EN);
else if (machine_is_hyacinth_1())
amba_clrbitsl(TIMER_CTR_REG, AMBARELLA_CE_TIMER_AXI1_CTR_EN);
#endif /* defined(CONFIG_MACH_HYACINTH_0) || defined(CONFIG_MACH_HYACINTH_1) */
}
static inline void ambarella_ce_timer_misc(void)
{
#if !defined(CONFIG_MACH_HYACINTH_0) && !defined(CONFIG_MACH_HYACINTH_1)
amba_setbitsl(TIMER_CTR_REG, AMBARELLA_CE_TIMER_CTR_OF);
amba_clrbitsl(TIMER_CTR_REG, AMBARELLA_CE_TIMER_CTR_CSL);
#else /* defined(CONFIG_MACH_HYACINTH_0) || defined(CONFIG_MACH_HYACINTH_1) */
if (machine_is_hyacinth_0()) {
amba_setbitsl(TIMER_CTR_REG, AMBARELLA_CE_TIMER_AXI0_CTR_OF);
amba_clrbitsl(TIMER_CTR_REG, AMBARELLA_CE_TIMER_AXI0_CTR_CSL);
}
else if (machine_is_hyacinth_1()) {
amba_setbitsl(TIMER_CTR_REG, AMBARELLA_CE_TIMER_AXI1_CTR_OF);
amba_clrbitsl(TIMER_CTR_REG, AMBARELLA_CE_TIMER_AXI1_CTR_CSL);
}
#endif /* defined(CONFIG_MACH_HYACINTH_0) || defined(CONFIG_MACH_HYACINTH_1) */
}
static void aucodec_digitalio_on_0(void)
{
/* aucodec_digitalio_on */
#if (CHIP_REV == A2S) || (CHIP_REV == A2M)
unsigned long flags;
ambarella_gpio_raw_lock(2, &flags);
amba_setbitsl(GPIO2_AFSEL_REG, (0xf << 18) | (0xf << 13));
ambarella_gpio_raw_unlock(2, &flags);
#elif (CHIP_REV == A2)
unsigned long flags;
ambarella_gpio_raw_lock(2, &flags);
amba_setbitsl(GPIO2_AFSEL_REG, (0x3 << 15) | (0x3 << 20));
ambarella_gpio_raw_unlock(2, &flags);
#elif (CHIP_REV == A3)||(CHIP_REV == A5)||(CHIP_REV == A6)|| \
(CHIP_REV == A5S)||(CHIP_REV == I1)
unsigned long flags;
ambarella_gpio_raw_lock(1, &flags);
amba_clrbitsl(GPIO1_AFSEL_REG, 0x80000000);
ambarella_gpio_raw_unlock(1, &flags);
/* GPIO77~GPIO81 program as hardware mode */
ambarella_gpio_raw_lock(2, &flags);
amba_setbitsl(GPIO2_AFSEL_REG, 0x0003e000);
ambarella_gpio_raw_unlock(2, &flags);
#elif (CHIP_REV == S2)
unsigned long flags;
ambarella_gpio_raw_lock(3, &flags);
amba_clrbitsl(GPIO3_AFSEL_REG, 0x00000030);
ambarella_gpio_raw_unlock(3, &flags);
/* GPIO77~GPIO81 program as hardware mode */
ambarella_gpio_raw_lock(2, &flags);
amba_setbitsl(GPIO2_AFSEL_REG, 0x0003e000);
ambarella_gpio_raw_unlock(2, &flags);
#else
pr_err("aucodec_digitalio_on: Unknown Chip Architecture\n");
#endif
}
int __init ambarella_init_fio(void)
{
#if defined(CONFIG_AMBARELLA_FIO_FORCE_SDIO_GPIO)
unsigned long flags;
//SMIO_38 ~ SMIO_43
ambarella_gpio_raw_lock(2, &flags);
amba_clrbitsl(GPIO2_AFSEL_REG, 0x000007e0);
amba_clrbitsl(GPIO2_DIR_REG, 0x00000780);
amba_setbitsl(GPIO2_DIR_REG, 0x00000060);
amba_writel(GPIO2_MASK_REG, 0x00000060);
amba_writel(GPIO2_DATA_REG, 0x00000040);
ambarella_gpio_raw_unlock(2, &flags);
#endif
return 0;
}
static void serial_ambarella_break_ctl(struct uart_port *port, int break_state)
{
unsigned long flags;
spin_lock_irqsave(&port->lock, flags);
if (break_state != 0)
amba_setbitsl(port->membase + UART_LC_OFFSET, UART_LC_BRK);
else
amba_clrbitsl(port->membase + UART_LC_OFFSET, UART_LC_BRK);
spin_unlock_irqrestore(&port->lock, flags);
}
static void serial_ambarella_shutdown(struct uart_port *port)
{
unsigned long flags;
free_irq(port->irq, port);
spin_lock_irqsave(&port->lock, flags);
amba_clrbitsl(port->membase + UART_LC_OFFSET, UART_LC_BRK);
amba_setbitsl(port->membase + UART_SRR_OFFSET, 0x01);
spin_unlock_irqrestore(&port->lock, flags);
}
static void ambench_apbread(void)
{
u64 raw_counter = 0;
u64 amba_counter = 0;
unsigned long flags;
disable_nonboot_cpus();
local_irq_save(flags);
amba_clrbitsl(TIMER_CTR_REG, TIMER_CTR_EN1);
amba_writel(TIMER1_STATUS_REG, APBREAD_RELOAD_NUM);
amba_writel(TIMER1_RELOAD_REG, 0x0);
amba_writel(TIMER1_MATCH1_REG, 0x0);
amba_writel(TIMER1_MATCH2_REG, 0x0);
amba_clrbitsl(TIMER_CTR_REG, TIMER_CTR_OF1);
amba_clrbitsl(TIMER_CTR_REG, TIMER_CTR_CSL1);
amba_setbitsl(TIMER_CTR_REG, TIMER_CTR_EN1);
do {
raw_counter++;
} while(__raw_readl((const volatile void *)TIMER1_STATUS_REG));
amba_clrbitsl(TIMER_CTR_REG, TIMER_CTR_EN1);
amba_writel(TIMER1_STATUS_REG, APBREAD_RELOAD_NUM);
amba_writel(TIMER1_RELOAD_REG, 0x0);
amba_writel(TIMER1_MATCH1_REG, 0x0);
amba_writel(TIMER1_MATCH2_REG, 0x0);
amba_clrbitsl(TIMER_CTR_REG, TIMER_CTR_OF1);
amba_clrbitsl(TIMER_CTR_REG, TIMER_CTR_CSL1);
amba_setbitsl(TIMER_CTR_REG, TIMER_CTR_EN1);
do {
amba_counter++;
} while(amba_readl(TIMER1_STATUS_REG));
amba_clrbitsl(TIMER_CTR_REG, TIMER_CTR_EN1);
local_irq_restore(flags);
enable_nonboot_cpus();
#if defined(CONFIG_PLAT_AMBARELLA_SUPPORT_HAL)
raw_counter *= get_apb_bus_freq_hz();
#else
raw_counter *= clk_get_rate(clk_get(NULL, "gclk_apb"));
#endif
do_div(raw_counter, APBREAD_RELOAD_NUM);
#if defined(CONFIG_PLAT_AMBARELLA_SUPPORT_HAL)
amba_counter *= get_apb_bus_freq_hz();
#else
amba_counter *= clk_get_rate(clk_get(NULL, "gclk_apb"));
#endif
do_div(amba_counter, APBREAD_RELOAD_NUM);
pr_info("CPU[0x%x] APBRead: raw speed %llu/s!\n",
cpu_architecture(), raw_counter);
pr_info("CPU[0x%x] APBRead: amba speed %llu/s!\n",
cpu_architecture(), amba_counter);
}
static int flush_rxfifo(void)
{
int retry_count = 1000;
int rval = 0;
#if (CHIP_REV == A2) || (CHIP_REV == A3)
retry_count = retry_count * 10;
if (!(amba_readl(USB_DEV_STS_REG) & USB_DEV_RXFIFO_EMPTY_STS)){
/* Switch to slave mode */
amba_clrbitsl(USB_DEV_CTRL_REG, USB_DEV_DMA_MD);
while (!(amba_readl(USB_DEV_STS_REG) & USB_DEV_RXFIFO_EMPTY_STS)) {
if (retry_count-- < 0) {
printk (KERN_ERR "%s: failed", __func__);
rval = -1;
break;
}
amba_readl(USB_RXFIFO_BASE);
udelay(5);
}
/* Switch to DMA mode */
amba_setbitsl(USB_DEV_CTRL_REG, USB_DEV_DMA_MD);
}
#else
amba_setbitsl(USB_DEV_CTRL_REG, USB_DEV_NAK);
amba_setbitsl(USB_DEV_CTRL_REG, USB_DEV_FLUSH_RXFIFO);
while(!(amba_readl(USB_DEV_STS_REG) & USB_DEV_RXFIFO_EMPTY_STS)) {
if (retry_count-- < 0) {
printk (KERN_ERR "%s: failed", __func__);
rval = -1;
break;
}
udelay(5);
}
amba_clrbitsl(USB_DEV_CTRL_REG, USB_DEV_NAK);
#endif
return rval;
}
int __init ambarella_init_fio(void)
{
fio_amb_exit_random_mode();
enable_fio_dma();
amba_writel(FLASH_INT_REG, 0x0);
amba_writel(XD_INT_REG, 0x0);
amba_writel(CF_STA_REG, CF_STA_CW | CF_STA_DW);
//#if defined(CONFIG_AMBARELLA_FIO_FORCE_SDIO_GPIO)
unsigned long flags;
//SMIO_38 ~ SMIO_43
ambarella_gpio_raw_lock(2, &flags);
amba_clrbitsl(GPIO2_AFSEL_REG, 0x000007e0);
amba_clrbitsl(GPIO2_DIR_REG, 0x00000780);
amba_setbitsl(GPIO2_DIR_REG, 0x00000060);
amba_writel(GPIO2_MASK_REG, 0x00000060);
amba_writel(GPIO2_DATA_REG, 0x00000040);
ambarella_gpio_raw_unlock(2, &flags);
//#endif
return 0;
}
static inline void ambarella_cs_timer_init(void)
{
#if defined(CONFIG_PLAT_AMBARELLA_SUPPORT_HAL)
#else
ambarella_register_clk(&pll_out_core);
ambarella_register_clk(&pll_out_idsp);
ambarella_register_clk(&gclk_core);
ambarella_register_clk(&gclk_ahb);
ambarella_register_clk(&gclk_apb);
#endif
#if !defined(CONFIG_MACH_HYACINTH_0) && !defined(CONFIG_MACH_HYACINTH_1)
amba_clrbitsl(TIMER_CTR_REG, AMBARELLA_CS_TIMER_CTR_EN);
amba_clrbitsl(TIMER_CTR_REG, AMBARELLA_CS_TIMER_CTR_OF);
amba_clrbitsl(TIMER_CTR_REG, AMBARELLA_CS_TIMER_CTR_CSL);
amba_writel(AMBARELLA_CS_TIMER_STATUS_REG, 0xffffffff);
amba_writel(AMBARELLA_CS_TIMER_RELOAD_REG, 0xffffffff);
amba_writel(AMBARELLA_CS_TIMER_MATCH1_REG, 0x0);
amba_writel(AMBARELLA_CS_TIMER_MATCH2_REG, 0x0);
amba_setbitsl(TIMER_CTR_REG, AMBARELLA_CS_TIMER_CTR_EN);
#else /* defined(CONFIG_MACH_HYACINTH_0) || defined(CONFIG_MACH_HYACINTH_1) */
if (machine_is_hyacinth_0()) {
amba_clrbitsl(TIMER_CTR_REG, AMBARELLA_CS_TIMER_AXI0_CTR_EN);
amba_clrbitsl(TIMER_CTR_REG, AMBARELLA_CS_TIMER_AXI0_CTR_OF);
amba_clrbitsl(TIMER_CTR_REG, AMBARELLA_CS_TIMER_AXI0_CTR_CSL);
amba_writel(AMBARELLA_CS_TIMER_AXI0_STATUS_REG, 0xffffffff);
amba_writel(AMBARELLA_CS_TIMER_AXI0_RELOAD_REG, 0xffffffff);
amba_writel(AMBARELLA_CS_TIMER_AXI0_MATCH1_REG, 0x0);
amba_writel(AMBARELLA_CS_TIMER_AXI0_MATCH2_REG, 0x0);
amba_setbitsl(TIMER_CTR_REG, AMBARELLA_CS_TIMER_AXI0_CTR_EN);
}
else if (machine_is_hyacinth_1()) {
amba_clrbitsl(TIMER_CTR_REG, AMBARELLA_CS_TIMER_AXI1_CTR_EN);
amba_clrbitsl(TIMER_CTR_REG, AMBARELLA_CS_TIMER_AXI1_CTR_OF);
amba_clrbitsl(TIMER_CTR_REG, AMBARELLA_CS_TIMER_AXI1_CTR_CSL);
amba_writel(AMBARELLA_CS_TIMER_AXI1_STATUS_REG, 0xffffffff);
amba_writel(AMBARELLA_CS_TIMER_AXI1_RELOAD_REG, 0xffffffff);
amba_writel(AMBARELLA_CS_TIMER_AXI1_MATCH1_REG, 0x0);
amba_writel(AMBARELLA_CS_TIMER_AXI1_MATCH2_REG, 0x0);
amba_setbitsl(TIMER_CTR_REG, AMBARELLA_CS_TIMER_AXI1_CTR_EN);
}
#endif /* defined(CONFIG_MACH_HYACINTH_0) || defined(CONFIG_MACH_HYACINTH_1) */
}
static void ambench_apbread(void)
{
u64 raw_counter = 0;
u64 amba_counter = 0;
unsigned long flags;
disable_nonboot_cpus();
local_irq_save(flags);
amba_clrbitsl(TIMER_CTR_REG, TIMER_CTR_EN1);
amba_writel(TIMER1_STATUS_REG, APBREAD_RELOAD_NUM);
amba_writel(TIMER1_RELOAD_REG, 0x0);
amba_writel(TIMER1_MATCH1_REG, 0x0);
amba_writel(TIMER1_MATCH2_REG, 0x0);
amba_clrbitsl(TIMER_CTR_REG, TIMER_CTR_OF1);
amba_clrbitsl(TIMER_CTR_REG, TIMER_CTR_CSL1);
amba_setbitsl(TIMER_CTR_REG, TIMER_CTR_EN1);
do {
raw_counter++;
} while(__raw_readl(TIMER1_STATUS_REG));
amba_clrbitsl(TIMER_CTR_REG, TIMER_CTR_EN1);
amba_writel(TIMER1_STATUS_REG, APBREAD_RELOAD_NUM);
amba_writel(TIMER1_RELOAD_REG, 0x0);
amba_writel(TIMER1_MATCH1_REG, 0x0);
amba_writel(TIMER1_MATCH2_REG, 0x0);
amba_clrbitsl(TIMER_CTR_REG, TIMER_CTR_OF1);
amba_clrbitsl(TIMER_CTR_REG, TIMER_CTR_CSL1);
amba_setbitsl(TIMER_CTR_REG, TIMER_CTR_EN1);
do {
amba_counter++;
} while(amba_readl(TIMER1_STATUS_REG));
amba_clrbitsl(TIMER_CTR_REG, TIMER_CTR_EN1);
local_irq_restore(flags);
enable_nonboot_cpus();
raw_counter *= get_apb_bus_freq_hz();
do_div(raw_counter, APBREAD_RELOAD_NUM);
amba_counter *= get_apb_bus_freq_hz();
do_div(amba_counter, APBREAD_RELOAD_NUM);
pr_info("CPU[0x%x] APBRead: raw speed %llu/s!\n",
cpu_architecture(), raw_counter);
pr_info("CPU[0x%x] APBRead: amba speed %llu/s!\n",
cpu_architecture(), amba_counter);
}
/* ==========================================================================*/
void __fio_select_lock(int module)
{
u32 fio_ctr;
u32 fio_dmactr;
#if (SD_HAS_INTERNAL_MUXER == 1)
unsigned long flags;
#endif
fio_ctr = amba_readl(FIO_CTR_REG);
fio_dmactr = amba_readl(FIO_DMACTR_REG);
switch (module) {
case SELECT_FIO_FL:
fio_ctr &= ~FIO_CTR_XD;
fio_dmactr = (fio_dmactr & 0xcfffffff) | FIO_DMACTR_FL;
break;
case SELECT_FIO_XD:
fio_ctr |= FIO_CTR_XD;
fio_dmactr = (fio_dmactr & 0xcfffffff) | FIO_DMACTR_XD;
break;
case SELECT_FIO_CF:
fio_ctr &= ~FIO_CTR_XD;
fio_dmactr = (fio_dmactr & 0xcfffffff) | FIO_DMACTR_CF;
#if (FIO_SUPPORT_AHB_CLK_ENA == 1)
fio_amb_sd2_disable();
fio_amb_cf_enable();
#endif
break;
case SELECT_FIO_SD:
fio_ctr &= ~FIO_CTR_XD;
fio_dmactr = (fio_dmactr & 0xcfffffff) | FIO_DMACTR_SD;
break;
case SELECT_FIO_SDIO:
fio_ctr |= FIO_CTR_XD;
fio_dmactr = (fio_dmactr & 0xcfffffff) | FIO_DMACTR_SD;
break;
case SELECT_FIO_SD2:
#if (FIO_SUPPORT_AHB_CLK_ENA == 1)
fio_amb_cf_disable();
fio_amb_sd2_enable();
#endif
#if (SD_HOST1_HOST2_HAS_MUX == 1)
fio_ctr &= ~FIO_CTR_XD;
fio_dmactr = (fio_dmactr & 0xcfffffff) | FIO_DMACTR_SD;
#endif
break;
default:
break;
}
#if (SD_HAS_INTERNAL_MUXER == 1)
spin_lock_irqsave(&fio_sd0_int_lock, flags);
amba_clrbitsl(SD_NISEN_REG, SD_NISEN_CARD);
spin_unlock_irqrestore(&fio_sd0_int_lock, flags);
#if defined(CONFIG_AMBARELLA_FIO_FORCE_SDIO_GPIO)
if (module != SELECT_FIO_SDIO) {
ambarella_gpio_raw_lock(2, &flags);
amba_clrbitsl(GPIO2_AFSEL_REG, 0x000007e0);
ambarella_gpio_raw_unlock(2, &flags);
}
#endif
#endif
amba_writel(FIO_CTR_REG, fio_ctr);
amba_writel(FIO_DMACTR_REG, fio_dmactr);
#if (SD_HAS_INTERNAL_MUXER == 1)
if (module == SELECT_FIO_SD) {
spin_lock_irqsave(&fio_sd0_int_lock, flags);
amba_writel(SD_NISEN_REG, fio_sd_int);
amba_writel(SD_NIXEN_REG, fio_sd_int);
spin_unlock_irqrestore(&fio_sd0_int_lock, flags);
} else
if (module == SELECT_FIO_SDIO) {
#if defined(CONFIG_AMBARELLA_FIO_FORCE_SDIO_GPIO)
ambarella_gpio_raw_lock(2, &flags);
amba_setbitsl(GPIO2_AFSEL_REG, 0x000007e0);
ambarella_gpio_raw_unlock(2, &flags);
#endif
spin_lock_irqsave(&fio_sd0_int_lock, flags);
amba_writel(SD_NISEN_REG, fio_sdio_int);
amba_writel(SD_NIXEN_REG, fio_sdio_int);
spin_unlock_irqrestore(&fio_sd0_int_lock, flags);
}
#endif
}
/* ==========================================================================*/
void __fio_select_lock(int module)
{
u32 fio_ctr;
u32 fio_dmactr;
fio_ctr = amba_readl(FIO_CTR_REG);
fio_dmactr = amba_readl(FIO_DMACTR_REG);
switch (module) {
case SELECT_FIO_FL:
fio_dmactr = (fio_dmactr & 0xcfffffff) | FIO_DMACTR_FL;
break;
case SELECT_FIO_XD:
fio_ctr |= FIO_CTR_XD;
fio_dmactr = (fio_dmactr & 0xcfffffff) | FIO_DMACTR_XD;
break;
case SELECT_FIO_CF:
fio_ctr &= ~FIO_CTR_XD;
fio_dmactr = (fio_dmactr & 0xcfffffff) | FIO_DMACTR_CF;
#if (FIO_SUPPORT_AHB_CLK_ENA == 1)
fio_amb_sd2_disable();
fio_amb_cf_enable();
#endif
break;
case SELECT_FIO_SD:
fio_ctr &= ~FIO_CTR_XD;
fio_dmactr = (fio_dmactr & 0xcfffffff) | FIO_DMACTR_SD;
break;
case SELECT_FIO_SDIO:
fio_ctr |= FIO_CTR_XD;
fio_dmactr = (fio_dmactr & 0xcfffffff) | FIO_DMACTR_SD;
break;
case SELECT_FIO_SD2:
#if (FIO_SUPPORT_AHB_CLK_ENA == 1)
fio_amb_cf_disable();
fio_amb_sd2_enable();
#endif
#if (CHIP_REV == A7L)
fio_ctr &= ~FIO_CTR_XD;
fio_dmactr = (fio_dmactr & 0xcfffffff) | FIO_DMACTR_SD;
#endif
break;
default:
break;
}
#if (SD_HAS_INTERNAL_MUXER == 1)
if (module != SELECT_FIO_SDIO) {
#if (HANDLE_SDIO_FAKE_IRQ == 1)
amba_clrbitsw(SD_NISEN_REG, SD_NISEN_CARD);
#endif
//SMIO_38 ~ SMIO_43
amba_clrbitsl(GPIO2_AFSEL_REG, 0x000007e0);
}
#endif
amba_writel(FIO_DMACTR_REG, fio_dmactr);
amba_writel(FIO_CTR_REG, fio_ctr);
#if (SD_HAS_INTERNAL_MUXER == 1)
if (module == SELECT_FIO_SDIO) {
//SMIO_38 ~ SMIO_43
amba_setbitsl(GPIO2_AFSEL_REG, 0x000007e0);
}
#endif
}
void fio_amb_exit_random_mode(void)
{
amba_clrbitsl(FIO_CTR_REG, FIO_CTR_RR);
}
void fio_amb_sd2_disable(void)
{
amba_clrbitsl(HOST_AHB_CLK_ENABLE_REG, HOST_AHB_SDIO_SEL);
}
void fio_amb_cf_disable(void)
{
amba_clrbitsl(HOST_AHB_CLK_ENABLE_REG, HOST_AHB_CF_CLK_ENB);
}
void fio_amb_fl_disable(void)
{
amba_clrbitsl(HOST_AHB_CLK_ENABLE_REG, HOST_AHB_FLASH_CLK_ENB);
}
static void __serial_ambarella_disable_ms(struct uart_port *port)
{
amba_clrbitsl(port->membase + UART_IE_OFFSET, UART_IE_EDSSI);
}
static void serial_ambarella_stop_rx(struct uart_port *port)
{
amba_clrbitsl(port->membase + UART_IE_OFFSET, UART_IE_ERBFI);
}
u32 ambarella_timer_resume(u32 level)
{
u32 timer_ctr_mask;
#if !defined(CONFIG_MACH_HYACINTH_0) && !defined(CONFIG_MACH_HYACINTH_1)
timer_ctr_mask = AMBARELLA_CE_TIMER_CTR_MASK;
#if defined(CONFIG_AMBARELLA_SUPPORT_CLOCKSOURCE)
timer_ctr_mask |= AMBARELLA_CS_TIMER_CTR_MASK;
#endif
amba_clrbitsl(TIMER_CTR_REG, timer_ctr_mask);
#if defined(CONFIG_AMBARELLA_SUPPORT_CLOCKSOURCE)
amba_writel(AMBARELLA_CS_TIMER_STATUS_REG,
ambarella_timer_pm.timer_cs_status_reg);
amba_writel(AMBARELLA_CS_TIMER_RELOAD_REG,
ambarella_timer_pm.timer_cs_reload_reg);
amba_writel(AMBARELLA_CS_TIMER_MATCH1_REG,
ambarella_timer_pm.timer_cs_match1_reg);
amba_writel(AMBARELLA_CS_TIMER_MATCH2_REG,
ambarella_timer_pm.timer_cs_match2_reg);
#endif
if ((ambarella_timer_pm.timer_ce_status_reg == 0) &&
(ambarella_timer_pm.timer_ce_reload_reg == 0)){
amba_writel(AMBARELLA_CE_TIMER_STATUS_REG,
AMBARELLA_TIMER_FREQ / HZ);
} else {
amba_writel(AMBARELLA_CE_TIMER_STATUS_REG,
ambarella_timer_pm.timer_ce_status_reg);
}
amba_writel(AMBARELLA_CE_TIMER_RELOAD_REG,
ambarella_timer_pm.timer_ce_reload_reg);
amba_writel(AMBARELLA_CE_TIMER_MATCH1_REG,
ambarella_timer_pm.timer_ce_match1_reg);
amba_writel(AMBARELLA_CE_TIMER_MATCH2_REG,
ambarella_timer_pm.timer_ce_match2_reg);
#else /* defined(CONFIG_MACH_HYACINTH_0) || defined(CONFIG_MACH_HYACINTH_1) */
if (machine_is_hyacinth_0()) {
timer_ctr_mask = AMBARELLA_CE_TIMER_AXI0_CTR_MASK;
#if defined(CONFIG_AMBARELLA_SUPPORT_CLOCKSOURCE)
timer_ctr_mask |= AMBARELLA_CS_TIMER_AXI0_CTR_MASK;
#endif
amba_clrbitsl(TIMER_CTR_REG, timer_ctr_mask);
#if defined(CONFIG_AMBARELLA_SUPPORT_CLOCKSOURCE)
amba_writel(AMBARELLA_CS_TIMER_AXI0_STATUS_REG,
ambarella_timer_pm.timer_cs_status_reg);
amba_writel(AMBARELLA_CS_TIMER_AXI0_RELOAD_REG,
ambarella_timer_pm.timer_cs_reload_reg);
amba_writel(AMBARELLA_CS_TIMER_AXI0_MATCH1_REG,
ambarella_timer_pm.timer_cs_match1_reg);
amba_writel(AMBARELLA_CS_TIMER_AXI0_MATCH2_REG,
ambarella_timer_pm.timer_cs_match2_reg);
#endif
if ((ambarella_timer_pm.timer_ce_status_reg == 0) &&
(ambarella_timer_pm.timer_ce_reload_reg == 0)){
amba_writel(AMBARELLA_CE_TIMER_AXI0_STATUS_REG,
AMBARELLA_TIMER_FREQ / HZ);
} else {
amba_writel(AMBARELLA_CE_TIMER_AXI0_STATUS_REG,
ambarella_timer_pm.timer_ce_status_reg);
}
amba_writel(AMBARELLA_CE_TIMER_AXI0_RELOAD_REG,
ambarella_timer_pm.timer_ce_reload_reg);
amba_writel(AMBARELLA_CE_TIMER_AXI0_MATCH1_REG,
ambarella_timer_pm.timer_ce_match1_reg);
amba_writel(AMBARELLA_CE_TIMER_AXI0_MATCH2_REG,
ambarella_timer_pm.timer_ce_match2_reg);
}
else if (machine_is_hyacinth_1()) {
timer_ctr_mask = AMBARELLA_CE_TIMER_AXI1_CTR_MASK;
#if defined(CONFIG_AMBARELLA_SUPPORT_CLOCKSOURCE)
timer_ctr_mask |= AMBARELLA_CS_TIMER_AXI1_CTR_MASK;
#endif
amba_clrbitsl(TIMER_CTR_REG, timer_ctr_mask);
#if defined(CONFIG_AMBARELLA_SUPPORT_CLOCKSOURCE)
amba_writel(AMBARELLA_CS_TIMER_AXI1_STATUS_REG,
ambarella_timer_pm.timer_cs_status_reg);
amba_writel(AMBARELLA_CS_TIMER_AXI1_RELOAD_REG,
ambarella_timer_pm.timer_cs_reload_reg);
amba_writel(AMBARELLA_CS_TIMER_AXI1_MATCH1_REG,
ambarella_timer_pm.timer_cs_match1_reg);
amba_writel(AMBARELLA_CS_TIMER_AXI1_MATCH2_REG,
ambarella_timer_pm.timer_cs_match2_reg);
#endif
if ((ambarella_timer_pm.timer_ce_status_reg == 0) &&
(ambarella_timer_pm.timer_ce_reload_reg == 0)){
amba_writel(AMBARELLA_CE_TIMER_AXI1_STATUS_REG,
AMBARELLA_TIMER_FREQ / HZ);
} else {
amba_writel(AMBARELLA_CE_TIMER_AXI1_STATUS_REG,
ambarella_timer_pm.timer_ce_status_reg);
}
amba_writel(AMBARELLA_CE_TIMER_AXI1_RELOAD_REG,
ambarella_timer_pm.timer_ce_reload_reg);
amba_writel(AMBARELLA_CE_TIMER_AXI1_MATCH1_REG,
ambarella_timer_pm.timer_ce_match1_reg);
amba_writel(AMBARELLA_CE_TIMER_AXI1_MATCH2_REG,
ambarella_timer_pm.timer_ce_match2_reg);
}
#endif /* defined(CONFIG_MACH_HYACINTH_0) || defined(CONFIG_MACH_HYACINTH_1) */
if (ambarella_timer_pm.timer_clk != AMBARELLA_TIMER_FREQ) {
clockevents_calc_mult_shift(&ambarella_clkevt,
AMBARELLA_TIMER_FREQ, 5);
ambarella_clkevt.max_delta_ns =
clockevent_delta2ns(0xffffffff, &ambarella_clkevt);
ambarella_clkevt.min_delta_ns =
clockevent_delta2ns(1, &ambarella_clkevt);
switch (ambarella_clkevt.mode) {
case CLOCK_EVT_MODE_PERIODIC:
ambarella_ce_timer_set_periodic();
break;
case CLOCK_EVT_MODE_ONESHOT:
case CLOCK_EVT_MODE_UNUSED:
case CLOCK_EVT_MODE_SHUTDOWN:
case CLOCK_EVT_MODE_RESUME:
break;
}
#if defined(CONFIG_AMBARELLA_SUPPORT_CLOCKSOURCE)
clocksource_change_rating(&ambarella_cs_timer_clksrc, 0);
ambarella_cs_timer_clksrc.mult = clocksource_hz2mult(
AMBARELLA_TIMER_FREQ, ambarella_cs_timer_clksrc.shift);
pr_debug("%s: mult = %u, shift = %u\n",
ambarella_cs_timer_clksrc.name,
ambarella_cs_timer_clksrc.mult,
ambarella_cs_timer_clksrc.shift);
clocksource_change_rating(&ambarella_cs_timer_clksrc,
AMBARELLA_TIMER_RATING);
#if defined(CONFIG_HAVE_SCHED_CLOCK)
setup_sched_clock(ambarella_read_sched_clock,
32, AMBARELLA_TIMER_FREQ);
#endif
#endif
}
#if !defined(CONFIG_MACH_HYACINTH_0) && !defined(CONFIG_MACH_HYACINTH_1)
timer_ctr_mask = AMBARELLA_CE_TIMER_CTR_MASK;
#if defined(CONFIG_AMBARELLA_SUPPORT_CLOCKSOURCE)
timer_ctr_mask |= AMBARELLA_CS_TIMER_CTR_MASK;
#endif
amba_setbitsl(TIMER_CTR_REG,
(ambarella_timer_pm.timer_ctr_reg & timer_ctr_mask));
if (level)
enable_irq(AMBARELLA_CE_TIMER_IRQ);
#else /* defined(CONFIG_MACH_HYACINTH_0) || defined(CONFIG_MACH_HYACINTH_1) */
if (machine_is_hyacinth_0()) {
timer_ctr_mask = AMBARELLA_CE_TIMER_AXI0_CTR_MASK;
#if defined(CONFIG_AMBARELLA_SUPPORT_CLOCKSOURCE)
timer_ctr_mask |= AMBARELLA_CS_TIMER_AXI0_CTR_MASK;
#endif
amba_setbitsl(TIMER_CTR_REG,
(ambarella_timer_pm.timer_ctr_reg & timer_ctr_mask));
if (level)
enable_irq(AMBARELLA_CE_TIMER_AXI0_IRQ);
}
else if (machine_is_hyacinth_1()) {
timer_ctr_mask = AMBARELLA_CE_TIMER_AXI1_CTR_MASK;
#if defined(CONFIG_AMBARELLA_SUPPORT_CLOCKSOURCE)
timer_ctr_mask |= AMBARELLA_CS_TIMER_AXI1_CTR_MASK;
#endif
amba_setbitsl(TIMER_CTR_REG,
(ambarella_timer_pm.timer_ctr_reg & timer_ctr_mask));
if (level)
enable_irq(AMBARELLA_CE_TIMER_AXI1_IRQ);
}
#endif /* defined(CONFIG_MACH_HYACINTH_0) || defined(CONFIG_MACH_HYACINTH_1) */
#if defined(CONFIG_SMP)
//percpu_timer_update_rate(amb_get_axi_clock_frequency(HAL_BASE_VP));
#endif
return 0;
}
u32 ambarella_timer_suspend(u32 level)
{
u32 timer_ctr_mask;
ambarella_timer_pm.timer_ctr_reg = amba_readl(TIMER_CTR_REG);
ambarella_timer_pm.timer_clk = AMBARELLA_TIMER_FREQ;
#if !defined(CONFIG_MACH_HYACINTH_0) && !defined(CONFIG_MACH_HYACINTH_1)
ambarella_timer_pm.timer_ce_status_reg =
amba_readl(AMBARELLA_CE_TIMER_STATUS_REG);
ambarella_timer_pm.timer_ce_reload_reg =
amba_readl(AMBARELLA_CE_TIMER_RELOAD_REG);
ambarella_timer_pm.timer_ce_match1_reg =
amba_readl(AMBARELLA_CE_TIMER_MATCH1_REG);
ambarella_timer_pm.timer_ce_match2_reg =
amba_readl(AMBARELLA_CE_TIMER_MATCH2_REG);
#if defined(CONFIG_AMBARELLA_SUPPORT_CLOCKSOURCE)
ambarella_timer_pm.timer_cs_status_reg =
amba_readl(AMBARELLA_CS_TIMER_STATUS_REG);
ambarella_timer_pm.timer_cs_reload_reg =
amba_readl(AMBARELLA_CS_TIMER_RELOAD_REG);
ambarella_timer_pm.timer_cs_match1_reg =
amba_readl(AMBARELLA_CS_TIMER_MATCH1_REG);
ambarella_timer_pm.timer_cs_match2_reg =
amba_readl(AMBARELLA_CS_TIMER_MATCH2_REG);
#endif
#else /* defined(CONFIG_MACH_HYACINTH_0) || defined(CONFIG_MACH_HYACINTH_1) */
if (machine_is_hyacinth_0()) {
ambarella_timer_pm.timer_ce_status_reg =
amba_readl(AMBARELLA_CE_TIMER_AXI0_STATUS_REG);
ambarella_timer_pm.timer_ce_reload_reg =
amba_readl(AMBARELLA_CE_TIMER_AXI0_RELOAD_REG);
ambarella_timer_pm.timer_ce_match1_reg =
amba_readl(AMBARELLA_CE_TIMER_AXI0_MATCH1_REG);
ambarella_timer_pm.timer_ce_match2_reg =
amba_readl(AMBARELLA_CE_TIMER_AXI0_MATCH2_REG);
#if defined(CONFIG_AMBARELLA_SUPPORT_CLOCKSOURCE)
ambarella_timer_pm.timer_cs_status_reg =
amba_readl(AMBARELLA_CS_TIMER_AXI0_STATUS_REG);
ambarella_timer_pm.timer_cs_reload_reg =
amba_readl(AMBARELLA_CS_TIMER_AXI0_RELOAD_REG);
ambarella_timer_pm.timer_cs_match1_reg =
amba_readl(AMBARELLA_CS_TIMER_AXI0_MATCH1_REG);
ambarella_timer_pm.timer_cs_match2_reg =
amba_readl(AMBARELLA_CS_TIMER_AXI0_MATCH2_REG);
#endif
}
else if (machine_is_hyacinth_1()) {
ambarella_timer_pm.timer_ce_status_reg =
amba_readl(AMBARELLA_CE_TIMER_AXI1_STATUS_REG);
ambarella_timer_pm.timer_ce_reload_reg =
amba_readl(AMBARELLA_CE_TIMER_AXI1_RELOAD_REG);
ambarella_timer_pm.timer_ce_match1_reg =
amba_readl(AMBARELLA_CE_TIMER_AXI1_MATCH1_REG);
ambarella_timer_pm.timer_ce_match2_reg =
amba_readl(AMBARELLA_CE_TIMER_AXI1_MATCH2_REG);
#if defined(CONFIG_AMBARELLA_SUPPORT_CLOCKSOURCE)
ambarella_timer_pm.timer_cs_status_reg =
amba_readl(AMBARELLA_CS_TIMER_AXI1_STATUS_REG);
ambarella_timer_pm.timer_cs_reload_reg =
amba_readl(AMBARELLA_CS_TIMER_AXI1_RELOAD_REG);
ambarella_timer_pm.timer_cs_match1_reg =
amba_readl(AMBARELLA_CS_TIMER_AXI1_MATCH1_REG);
ambarella_timer_pm.timer_cs_match2_reg =
amba_readl(AMBARELLA_CS_TIMER_AXI1_MATCH2_REG);
#endif
}
#endif /* defined(CONFIG_MACH_HYACINTH_0) || defined(CONFIG_MACH_HYACINTH_1) */
if (level) {
#if !defined(CONFIG_MACH_HYACINTH_0) && !defined(CONFIG_MACH_HYACINTH_1)
disable_irq(AMBARELLA_CE_TIMER_IRQ);
timer_ctr_mask = AMBARELLA_CE_TIMER_CTR_MASK;
#if defined(CONFIG_AMBARELLA_SUPPORT_CLOCKSOURCE)
timer_ctr_mask |= AMBARELLA_CS_TIMER_CTR_MASK;
#endif
#else /* defined(CONFIG_MACH_HYACINTH_0) || defined(CONFIG_MACH_HYACINTH_1) */
if (machine_is_hyacinth_0()) {
disable_irq(AMBARELLA_CE_TIMER_AXI0_IRQ);
timer_ctr_mask = AMBARELLA_CE_TIMER_AXI0_CTR_MASK;
#if defined(CONFIG_AMBARELLA_SUPPORT_CLOCKSOURCE)
timer_ctr_mask |= AMBARELLA_CS_TIMER_AXI0_CTR_MASK;
#endif
}
else if (machine_is_hyacinth_1()) {
disable_irq(AMBARELLA_CE_TIMER_AXI1_IRQ);
timer_ctr_mask = AMBARELLA_CE_TIMER_AXI1_CTR_MASK;
#if defined(CONFIG_AMBARELLA_SUPPORT_CLOCKSOURCE)
timer_ctr_mask |= AMBARELLA_CS_TIMER_AXI1_CTR_MASK;
#endif
}
#endif /* defined(CONFIG_MACH_HYACINTH_0) || defined(CONFIG_MACH_HYACINTH_1) */
amba_clrbitsl(TIMER_CTR_REG, timer_ctr_mask);
}
return 0;
}
