int gpio_amlogic_direction_output(struct gpio_chip *chip,unsigned offset, int value) { unsigned int reg,bit; if(offset==GPIO_BSD_EN){ aml_clr_reg32_mask(P_PREG_PAD_GPIO0_O,1<<29); #ifndef CONFIG_MESON_TRUSTZONE aml_set_reg32_mask(P_AO_SECURE_REG0,1<<0); #else meson_secure_reg_write(P_AO_SECURE_REG0, meson_secure_reg_read(P_AO_SECURE_REG0) | (1<<0)); #endif if(value) aml_set_reg32_mask(P_PREG_PAD_GPIO0_O,1<<31);//out put high else aml_clr_reg32_mask(P_PREG_PAD_GPIO0_O,1<<31);//out put low aml_clr_reg32_mask(P_PREG_PAD_GPIO0_O,1<<30);//out put enable return 0; } if(offset==GPIO_TEST_N){ if(value) aml_set_reg32_mask(P_AO_GPIO_O_EN_N,1<<31);//out put high else aml_clr_reg32_mask(P_AO_GPIO_O_EN_N,1<<31);//out put low #ifndef CONFIG_MESON_TRUSTZONE aml_set_reg32_mask(P_AO_SECURE_REG0,1);// out put enable #else meson_secure_reg_write(P_AO_SECURE_REG0, meson_secure_reg_read(P_AO_SECURE_REG0) | (1<<0)); #endif return 0; } if(value){ reg=GPIO_REG(amlogic_pins[offset].out_value_reg_bit); bit=GPIO_BIT(amlogic_pins[offset].out_value_reg_bit); aml_set_reg32_mask(p_gpio_output_addr[reg],1<<bit); gpio_print("out reg=%x,value=%x\n",p_gpio_output_addr[reg],aml_read_reg32(p_gpio_output_addr[reg])); } else{ reg=GPIO_REG(amlogic_pins[offset].out_value_reg_bit); bit=GPIO_BIT(amlogic_pins[offset].out_value_reg_bit); aml_clr_reg32_mask(p_gpio_output_addr[reg],1<<bit); gpio_print("out reg=%x,value=%x\n",p_gpio_output_addr[reg],aml_read_reg32(p_gpio_output_addr[reg])); } reg=GPIO_REG(amlogic_pins[offset].out_en_reg_bit); bit=GPIO_BIT(amlogic_pins[offset].out_en_reg_bit); aml_clr_reg32_mask(p_gpio_oen_addr[reg],1<<bit); gpio_print("==%s==%d\n",__FUNCTION__,__LINE__); gpio_print("oen reg=%x,value=%x\n",p_gpio_oen_addr[reg],aml_read_reg32(p_gpio_oen_addr[reg])); gpio_print("value=%d\n",value); return 0; }
static void __init meson_clocksource_init(void) { aml_clr_reg32_mask(P_ISA_TIMER_MUX, TIMER_E_INPUT_MASK); aml_set_reg32_mask(P_ISA_TIMER_MUX, TIMERE_UNIT_1us << TIMER_E_INPUT_BIT); /// aml_write_reg32(P_ISA_TIMERE, 0); /** * (counter*mult)>>shift=xxx ns */ /** * Constants generated by clocks_calc_mult_shift(m, s, 1MHz, NSEC_PER_SEC, 0). * This gives a resolution of about 1us and a wrap period of about 1h11min. */ clocksource_timer_e.shift = 22; clocksource_timer_e.mult = 4194304000u; clocksource_register(&clocksource_timer_e); clocksource_timer_f.shift = 22; clocksource_timer_f.mult = 3790016000u; clocksource_register(&clocksource_timer_f); init_fixed_sched_clock(&cd, meson6_update_sched_clock, 32, USEC_PER_SEC, clocksource_timer_e.mult, clocksource_timer_e.shift); }
void malifix_init(void) { #if MESON_CPU_TYPE == MESON_CPU_TYPE_MESON6 if (!mali_meson_is_revb()) return; if ((mali_mm1_regs) && (mali_mm2_regs)) return; mali_mmu_int_process_state[0] = 0; mali_mmu_int_process_state[1] = 0; /* set up Timer C as a 1uS one-shot timer */ aml_clr_reg32_mask(P_ISA_TIMER_MUX, (1<<18)|(1<<14)|(3<<4)); aml_set_reg32_mask(P_ISA_TIMER_MUX, (1<<18)|(0<<14)|(0<<4)); setup_timer(&timer, timer_callback, 0); mali_mm1_regs = (ulong *)ioremap_nocache(MALI_MM1_REG_ADDR, MALI_MM_REG_SIZE); if (mali_mm1_regs) printk("Mali pp1 MMU register mapped at %p...\n", mali_mm1_regs); mali_mm2_regs = (ulong *)ioremap_nocache(MALI_MM2_REG_ADDR, MALI_MM_REG_SIZE); if (mali_mm2_regs) printk("Mali pp2 MMU register mapped at %p...\n", mali_mm2_regs); if ((mali_mm1_regs != NULL) && (mali_mm2_regs != NULL)) mod_timer(&timer, jiffies + HZ/100); #endif }
int amlogic_pin_config_group_set(struct pinctrl_dev *pctldev, unsigned group, unsigned long config) { unsigned reg,bit,ret=-1,i; struct amlogic_pmx *apmx = pinctrl_dev_get_drvdata(pctldev); u16 pullparam = AML_PINCONF_UNPACK_PULL_PARA(config); u16 oenparam = AML_PINCONF_UNPACK_ENOUT_PARA(config); u16 oenarg = AML_PINCONF_UNPACK_ENOUT_ARG(config); const struct amlogic_pin_group *pin_group=&apmx->soc->groups[group]; const unsigned int *pins=pin_group->pins; const unsigned int num_pins=pin_group->num_pins; dbg_print("config=0x%x\n",config); if(AML_PCON_PULLUP==pullparam) { for(i=0;i<num_pins;i++){ ret=apmx->soc->meson_set_pullup(pins[i],config); } } if(AML_PCON_ENOUT==oenparam) { for(i=0;i<num_pins;i++){ ret=apmx->soc->pin_map_to_direction(pins[i],®,&bit); dbg_print("pin[%d]=%d,reg=%d,bit=%d\n",i,pins[i],reg,bit); if(!ret) { if(oenarg) aml_set_reg32_mask(p_gpio_oen_addr[reg],1<<bit); else aml_clr_reg32_mask(p_gpio_oen_addr[reg],1<<bit); } } } return ret; }
static int osd_hw_setup(logo_object_t *plogo) { struct osd_ctl_s osd_ctl; const color_bit_define_t *color; osd_ctl.addr=plogo->dev->output_dev.osd.mem_start; osd_ctl.index=plogo->dev->idx; plogo->dev->output_dev.osd.color_depth=plogo->parser->logo_pic_info.color_info; color=&default_color_format_array[plogo->dev->output_dev.osd.color_depth]; osd_ctl.xres=plogo->dev->vinfo->width ; //logo pic. osd_ctl.yres=plogo->dev->vinfo->height; osd_ctl.xres_virtual=plogo->dev->vinfo->width ; osd_ctl.yres_virtual=plogo->dev->vinfo->height<<1; osd_ctl.disp_start_x=0; osd_ctl.disp_end_x=osd_ctl.xres -1; osd_ctl.disp_start_y=0; osd_ctl.disp_end_y=osd_ctl.yres-1; osd_init_hw(0); setup_color_mode(color,osd_ctl.index==0?P_VIU_OSD1_BLK0_CFG_W0:P_VIU_OSD2_BLK0_CFG_W0); if(!plogo->para.loaded) { if(plogo->dev->idx == LOGO_DEV_OSD0){ aml_set_reg32_mask(P_VPP_MISC,VPP_OSD1_POSTBLEND); }else if(plogo->dev->idx == LOGO_DEV_OSD1){ aml_set_reg32_mask(P_VPP_MISC,VPP_OSD2_POSTBLEND); } } osd_setup(&osd_ctl, \ 0, \ 0, \ osd_ctl.xres, \ osd_ctl.yres, \ osd_ctl.xres_virtual, \ osd_ctl.yres_virtual, \ osd_ctl.disp_start_x, \ osd_ctl.disp_start_y, \ osd_ctl.disp_end_x, \ osd_ctl.disp_end_y, \ osd_ctl.addr, \ color, \ osd_ctl.index) ; return SUCCESS; }
int gpio_amlogic_direction_input(struct gpio_chip *chip,unsigned offset) { unsigned int reg,bit; gpio_print("==%s==%d\n",__FUNCTION__,__LINE__); reg=GPIO_REG(amlogic_pins[offset].out_en_reg_bit); bit=GPIO_BIT(amlogic_pins[offset].out_en_reg_bit); aml_set_reg32_mask(p_gpio_oen_addr[reg],1<<bit); return 0; }
void power_init_off(void) { #if 0 aml_clr_reg32_mask(P_HHI_DEMOD_CLK_CNTL, (1 << 8)); aml_clr_reg32_mask(P_HHI_SATA_CLK_CNTL, (1 << 8)); aml_clr_reg32_mask(P_HHI_ETH_CLK_CNTL, (1 << 8)); aml_clr_reg32_mask(P_HHI_WIFI_CLK_CNTL, (1 << 0)); aml_set_reg32_mask(P_HHI_DEMOD_PLL_CNTL, (1 << 15)); #endif }
void gpio_amlogic_set(struct gpio_chip *chip,unsigned offset, int value) { unsigned int reg,bit; reg=GPIO_REG(amlogic_pins[offset].out_value_reg_bit); bit=GPIO_BIT(amlogic_pins[offset].out_value_reg_bit); gpio_print("==%s==%d\n",__FUNCTION__,__LINE__); if(value) aml_set_reg32_mask(p_gpio_output_addr[reg],1<<bit); else aml_clr_reg32_mask(p_gpio_output_addr[reg],1<<bit); }
static int m8b_set_pullup(unsigned int pin,unsigned int val,unsigned int pullen) { unsigned int reg=0,bit=0,bit_en=0,ret; ret=m8b_pin_to_pullup(pin,®,&bit,&bit_en); if(!ret) { if(pullen){ if(!ret) { if(val) aml_set_reg32_mask(p_pull_up_addr[reg],1<<bit); else aml_clr_reg32_mask(p_pull_up_addr[reg],1<<bit); } aml_set_reg32_mask(p_pull_upen_addr[reg],1<<bit_en); } else aml_clr_reg32_mask(p_pull_upen_addr[reg],1<<bit_en); } return ret; }
static int m6_set_pullup(unsigned int pin,unsigned int config) { unsigned int reg=0,bit=0,ret; u16 pullarg = AML_PINCONF_UNPACK_PULL_ARG(config); ret=amlogic_pin_to_pullup(pin,®,&bit); if(!ret) { if(pullarg) aml_set_reg32_mask(p_pull_up_addr[reg],1<<bit); else aml_clr_reg32_mask(p_pull_up_addr[reg],1<<bit); } return ret; }
void clk_switch(int flag) { int i; int clk_count=sizeof(clks)/sizeof(clks[0]); unsigned int uart_rate_clk; if (flag) { for (i = clk_count - 1; i >= 0; i--) { if (clks[i].clk_flag) { if (clks[i].clk_addr == P_HHI_MPEG_CLK_CNTL) { uart_rate_clk = clk_get_rate(clk81); wait_uart_empty(); aml_set_reg32_mask(clks[i].clk_addr,(1<<7));//gate on pll udelay(10); aml_set_reg32_mask(clks[i].clk_addr,(1<<8));//switch to pll udelay(10); uart_change_buad(P_AO_UART_REG5,uart_rate_clk); clks[i].clk_flag = 0; } printk(KERN_INFO "clk %s(%x) on\n", clks[i].clk_name, ((clks[i].clk_addr)&0xffff)>>2); } } } else { for (i = 0; i < clk_count; i++) {
static void __init meson_clocksource_init(void) { aml_clr_reg32_mask(P_ISA_TIMER_MUX, TIMER_E_INPUT_MASK); aml_set_reg32_mask(P_ISA_TIMER_MUX, TIMERE_UNIT_1us << TIMER_E_INPUT_BIT); /// aml_write_reg32(P_ISA_TIMERE, 0); /** * (counter*mult)>>shift=xxx ns */ clocksource_timer_e.shift = 0; clocksource_timer_e.mult = 1000; clocksource_register(&clocksource_timer_e); }
static int m6tv_set_pullup(unsigned int pin, unsigned int config) { unsigned int reg = 0, bit = 0, ret; u16 pullarg = AML_PINCONF_UNPACK_PULL_ARG(config); if (m6tv_pull_up[pin] == PULL_UP_NONE) return -1; reg = PULL_UP_REG(m6tv_pull_up[pin]); bit = PULL_UP_BIT(m6tv_pull_up[pin]); if(pullarg) aml_set_reg32_mask(p_pull_up_addr[reg], 1<<bit); else aml_clr_reg32_mask(p_pull_up_addr[reg], 1<<bit); return 0; }
static void aml_audio_clock_gating_enable(void) { #ifdef _AML_PCM_DEBUG_ printk("***Entered %s:%s\n", __FILE__,__func__); #endif /* aml_set_reg32_mask(P_HHI_GCLK_MPEG0, (1<<18)); aml_set_reg32_mask(P_HHI_GCLK_MPEG1, (1<<2) |(0xba<<6) ); aml_set_reg32_mask(P_HHI_GCLK_OTHER, (1<<18) |(0x6<<14) ); */ aml_set_reg32_mask( P_HHI_AUD_CLK_CNTL, (1 << 8)); //printk("P_HHI_GCLK_MPEG0=enable--%#x\n\n", aml_read_reg32(P_HHI_GCLK_MPEG0)); //printk("P_HHI_GCLK_MPEG1=enable--%#x\n\n", aml_read_reg32(P_HHI_GCLK_MPEG1)); //printk("P_HHI_GCLK_OTHER=enable--%#x\n\n", aml_read_reg32(P_HHI_GCLK_OTHER)); }
static int amlogic_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector, unsigned group) { struct amlogic_pmx *apmx=pinctrl_dev_get_drvdata(pctldev); int i; struct amlogic_pin_group *pin_group=&apmx->soc->groups[group]; struct amlogic_reg_mask *setmask=pin_group->setmask; struct amlogic_reg_mask *clrmask=pin_group->clearmask; for(i=0;i<pin_group->num_clearmask;i++){ aml_clr_reg32_mask(p_pin_mux_reg_addr[clrmask[i].reg],clrmask[i].mask); dbg_print("clear reg=%x,mask=%x\n",clrmask[i].reg,clrmask[i].mask); } for(i=0;i<pin_group->num_setmask;i++){ aml_set_reg32_mask(p_pin_mux_reg_addr[setmask[i].reg],setmask[i].mask); dbg_print("set reg=%d,mask=0x%x\n",setmask[i].reg,setmask[i].mask); } return 0; }
int board_init(void) { #ifdef CONFIG_M201_COSTDOWN /* pull up Linux rx/tx */ writel(readl(P_AO_RTI_PULL_UP_REG) | (3 << 0 | 3 << 16), P_AO_RTI_PULL_UP_REG); #endif borad_power_init(); gd->bd->bi_arch_number=MACH_TYPE_MESON6_SKT; gd->bd->bi_boot_params=BOOT_PARAMS_OFFSET; #if CONFIG_JERRY_NAND_TEST //temp test nand_init(); #endif #ifdef CONFIG_AML_I2C board_i2c_init(); #endif /*CONFIG_AML_I2C*/ #ifdef CONFIG_IR_REMOTE board_ir_init(); #endif #ifdef CONFIG_USB_DWC_OTG_HCD board_usb_init(&g_usb_config_m6_skt_b,BOARD_USB_MODE_HOST); board_usb_init(&g_usb_config_m6_skt_h,BOARD_USB_MODE_CHARGER); #endif /*CONFIG_USB_DWC_OTG_HCD*/ #ifdef CONFIG_M201_COSTDOWN /* 32k clock init */ printf("init 32k clock\n"); aml_set_reg32_mask(P_PERIPHS_PIN_MUX_9,0x1<<19);//set mode GPIOX_10-->CLK_OUT3 WRITE_CBUS_REG(PWM_PWM_E, 0x16d016d); WRITE_CBUS_REG(PWM_MISC_REG_EF, 0x8001); /* init led out put */ //red off gpio_amlogic_requst(NULL, GPIOAO_2); gpio_amlogic_direction_output(NULL, GPIOAO_2, 1); //green on gpio_amlogic_requst(NULL, GPIOAO_13); gpio_amlogic_direction_output(NULL, GPIOAO_13, 0); #endif return 0; }
static int am_uart_startup(struct uart_port *port) { unsigned long mode; struct meson_uart_port * mup = &am_ports[port->line]; am_uart_t *uart = mup->uart; mutex_init(&mup->info_mutex); mutex_lock(&mup->info_mutex); aml_set_reg32_mask((uint32_t)&uart->mode, UART_RXRST|UART_TXRST|UART_CLEAR_ERR); aml_clr_reg32_mask((uint32_t)&uart->mode, UART_RXRST|UART_TXRST|UART_CLEAR_ERR); mode = readl(&uart->mode); mode |= UART_RXENB | UART_TXENB; writel(mode, &uart->mode); mutex_unlock(&mup->info_mutex); //meson_uart_start_port(mup); return 0; }
static int snd_request_hw_timer(void *data) { int ret = 0; mutex_lock(&timer_mutex); if (hw_timer_init == 0) { aml_clr_reg32_mask(P_ISA_TIMER_MUX, ((3 << 0) | (1 << 15) | (1 << 19))); aml_set_reg32_mask(P_ISA_TIMER_MUX, ((TIMERB_RESOLUTION << 0) | (TIMERB_MODE << 15) | (1 << 19))); aml_write_reg32(P_ISA_TIMERD, TIMER_COUNT); hw_timer_init = 1; } mutex_unlock(&timer_mutex); ret = request_irq(INT_TIMER_D, audio_isr_handler, IRQF_SHARED, "timerd_irq", data); if (ret < 0) { printk("audio hw interrupt register fail \n"); return -1; } return 0; }
static void __init meson_clocksource_init(void) { aml_clr_reg32_mask(P_ISA_TIMER_MUX, TIMER_E_RESOLUTION_MASK); aml_set_reg32_mask(P_ISA_TIMER_MUX, TIMER_E_RESOLUTION_1us << TIMER_E_RESOLUTION_BIT); /// aml_write_reg32(P_ISA_TIMERE, 0); /** * (counter*mult)>>shift=xxx ns */ /** * Constants generated by clocks_calc_mult_shift(m, s, 1MHz, NSEC_PER_SEC, 0). * This gives a resolution of about 1us and a wrap period of about 1h11min. */ clocksource_timer_e.shift = 22; clocksource_timer_e.mult = 4194304000u; clocksource_register_khz(&clocksource_timer_e,1000); setup_sched_clock(meson8_read_sched_clock, 32,USEC_PER_SEC); }
static void ir_hardware_init(void) { unsigned int control_value; rec_idx = 0; last_jiffies = 0xffffffff; //mask--mux gpio_A07 to remote aml_set_reg32_mask(AOBUS_REG_ADDR(AO_RTI_PIN_MUX_REG),1<<0); //max frame time is 80ms, base rate is 2us control_value = 3<<28|(0x9c40 << 12)|0x1; am_remote_write_reg(AM_IR_DEC_REG0, control_value); /*[3-2]rising or falling edge detected [8-7]Measure mode */ control_value = 0x8574; am_remote_write_reg(AM_IR_DEC_REG1, control_value); request_fiq(INT_REMOTE, &ir_fiq_interrupt); }
static int _switch_gate(mod_type_t type, int flag) { int ret = 0; switch(type) { case MOD_VDEC: PRINT_INFO("turn %s vdec module\n", flag?"on":"off"); if (flag) { GATE_ON(DOS); aml_set_reg32_mask(P_HHI_VDEC_CLK_CNTL, 1 << 8); } else { GATE_OFF(DOS); aml_clr_reg32_mask(P_HHI_VDEC_CLK_CNTL, 1 << 8); } break; case MOD_AUDIO: PRINT_INFO("turn %s audio module\n", flag?"on":"off"); if (flag) { GATE_ON(AIU_AMCLK_MEASURE); GATE_ON(AIU_AIFIFO2); GATE_ON(AIU_AUD_MIXER); GATE_ON(AIU_MIXER_REG); GATE_ON(AIU_IEC958); GATE_ON(AIU_AI_TOP_GLUE); GATE_ON(AUD_BUF); GATE_ON(AIU_I2S_OUT); GATE_ON(AIU_AMCLK); //this gate should not be turned off GATE_ON(AIU_ICE958_AMCLK); GATE_ON(AIU_AOCLK); //GATE_ON(AUD_IN); GATE_ON(AIU_ADC); GATE_ON(AIU_AUDIN_SCLK); } else { GATE_OFF(AIU_AMCLK_MEASURE); GATE_OFF(AIU_AIFIFO2); GATE_OFF(AIU_AUD_MIXER); GATE_OFF(AIU_MIXER_REG); GATE_OFF(AIU_IEC958); GATE_OFF(AIU_AI_TOP_GLUE); GATE_OFF(AUD_BUF); GATE_OFF(AIU_I2S_OUT); GATE_OFF(AIU_AMCLK); //this gate should not be turned off GATE_OFF(AIU_ICE958_AMCLK); GATE_OFF(AIU_AOCLK); //GATE_OFF(AUD_IN); GATE_OFF(AIU_ADC); GATE_OFF(AIU_AUDIN_SCLK); } break; case MOD_HDMI: PRINT_INFO("turn %s hdmi module\n", flag?"on":"off"); if (flag) { GATE_ON(HDMI_INTR_SYNC); GATE_ON(HDMI_PCLK); GATE_ON(VCLK1_HDMI); } else { GATE_OFF(HDMI_INTR_SYNC); GATE_OFF(HDMI_PCLK); GATE_OFF(VCLK1_HDMI); } break; case MOD_VENC: PRINT_INFO("turn %s venc module\n", flag?"on":"off"); if (flag) { GATE_ON(VCLK2_VENCI); GATE_ON(VCLK2_VENCI1); GATE_ON(VCLK2_VENCP); GATE_ON(VCLK2_VENCP1); GATE_ON(VENC_P_TOP); GATE_ON(VENC_I_TOP); GATE_ON(VENCI_INT); GATE_ON(VENCP_INT); GATE_ON(VCLK2_ENCI); GATE_ON(VCLK2_ENCP); GATE_ON(VCLK2_VENCT); GATE_ON(VCLK2_VENCT1); GATE_ON(VCLK2_OTHER); GATE_ON(VCLK2_OTHER1); GATE_ON(ENC480P); GATE_ON(VENC_DAC); GATE_ON(DAC_CLK); } else { GATE_OFF(VCLK2_VENCI); GATE_OFF(VCLK2_VENCI1); GATE_OFF(VCLK2_VENCP); #if !defined(CONFIG_MESON_POWER_PROFILE_LOW) GATE_OFF(VCLK2_VENCP1); GATE_OFF(VENC_P_TOP); GATE_OFF(VENC_I_TOP); #endif GATE_OFF(VENCI_INT); #if !defined(CONFIG_MESON_POWER_PROFILE_LOW) GATE_OFF(VENCP_INT); #endif GATE_OFF(VCLK2_ENCI); #if !defined(CONFIG_MESON_POWER_PROFILE_LOW) GATE_OFF(VCLK2_ENCP); #endif GATE_OFF(VCLK2_VENCT); GATE_OFF(VCLK2_VENCT1); GATE_OFF(VCLK2_OTHER); GATE_OFF(VCLK2_OTHER1); GATE_OFF(ENC480P); #if !defined(CONFIG_MESON_POWER_PROFILE_LOW) GATE_OFF(VENC_DAC); #endif GATE_OFF(DAC_CLK); } break; case MOD_TCON: PRINT_INFO("turn %s tcon module\n", flag?"on":"off"); if (flag) { GATE_ON(VENC_T_TOP); GATE_ON(VENCT_INT); GATE_ON(VCLK2_ENCT); } else { GATE_OFF(VENC_T_TOP); GATE_OFF(VENCT_INT); GATE_OFF(VCLK2_ENCT); } break; case MOD_LVDS: PRINT_INFO("turn %s lvds module\n", flag?"on":"off"); if (flag) { GATE_ON(VENC_L_TOP); GATE_ON(VENCL_INT); GATE_ON(VCLK2_ENCL); } else { GATE_OFF(VENC_L_TOP); GATE_OFF(VENCL_INT); GATE_OFF(VCLK2_ENCL); } break; case MOD_MIPI: PRINT_INFO("turn %s mipi module\n", flag?"on":"off"); if (flag) { GATE_ON(MIPI_APB_CLK); GATE_ON(MIPI_SYS_CLK); GATE_ON(MIPI_PHY); } else { GATE_OFF(MIPI_APB_CLK); GATE_OFF(MIPI_SYS_CLK); GATE_OFF(MIPI_PHY); } break; case MOD_BT656: PRINT_INFO("turn %s bt656 module\n", flag?"on":"off"); if (flag) { GATE_ON(BT656_IN); } else { GATE_OFF(BT656_IN); } break; case MOD_SPI: PRINT_INFO("turn %s spi module\n", flag?"on":"off"); if (flag) { GATE_ON(SPICC); GATE_ON(SPI1); GATE_ON(SPI2); } else { GATE_OFF(SPICC); GATE_OFF(SPI1); GATE_OFF(SPI2); } break; case MOD_UART0: PRINT_INFO("turn %s uart0 module\n", flag?"on":"off"); if (flag) { GATE_ON(UART0); } else { GATE_OFF(UART0); } break; case MOD_UART1: PRINT_INFO("turn %s uart1 module\n", flag?"on":"off"); if (flag) { GATE_ON(UART1); } else { GATE_OFF(UART1); } break; case MOD_UART2: PRINT_INFO("turn %s uart2 module\n", flag?"on":"off"); if (flag) { GATE_ON(UART2); } else { GATE_OFF(UART2); } break; case MOD_UART3: PRINT_INFO("turn %s uart3 module\n", flag?"on":"off"); if (flag) { GATE_ON(UART3); } else { GATE_OFF(UART3); } break; case MOD_ROM: PRINT_INFO("turn %s rom module\n", flag?"on":"off"); if (flag) { GATE_ON(ROM_CLK); } else { GATE_OFF(ROM_CLK); } break; case MOD_EFUSE: PRINT_INFO("turn %s efuse module\n", flag?"on":"off"); if (flag) { GATE_ON(EFUSE); } else { GATE_OFF(EFUSE); } break; case MOD_RANDOM_NUM_GEN: PRINT_INFO("turn %s random_num_gen module\n", flag?"on":"off"); if (flag) { GATE_ON(RANDOM_NUM_GEN); } else { GATE_OFF(RANDOM_NUM_GEN); } break; case MOD_ETHERNET: PRINT_INFO("turn %s ethernet module\n", flag?"on":"off"); if (flag) { GATE_ON(ETHERNET); } else { GATE_OFF(ETHERNET); } break; case MOD_MEDIA_CPU: PRINT_INFO("trun %s Audio DSP\n", flag? " on" : "off"); if(flag){ GATE_ON(MEDIA_CPU); }else{ GATE_OFF(MEDIA_CPU); } break; case MOD_GE2D: PRINT_INFO("trun %s GE2D\n", flag? " on" : "off"); if(flag){ GATE_ON(GE2D); }else{ GATE_OFF(GE2D); } break; case MOD_VIDEO_IN: PRINT_INFO("trun %s video_in\n", flag? " on" : "off"); if(flag){ GATE_ON(VIDEO_IN); }else{ GATE_OFF(VIDEO_IN); } break; case MOD_VIU2: PRINT_INFO("trun %s viu2\n", flag? " on" : "off"); if(flag){ GATE_ON(VIU2); }else{ GATE_OFF(VIU2); } break; case MOD_AUD_IN: PRINT_INFO("trun %s audio_in\n", flag? " on" : "off"); #if 0 if(flag){ GATE_ON(AIU_ADC); GATE_ON(AIU_AUDIN_SCLK); }else{ GATE_OFF(AIU_ADC); GATE_OFF(AIU_AUDIN_SCLK); } #endif break; case MOD_AUD_OUT: PRINT_INFO("trun %s audio_out\n", flag? " on" : "off"); if(flag){ }else{ } break; case MOD_AHB: PRINT_INFO("trun %s ahb\n", flag? " on" : "off"); if(flag){ GATE_ON(AHB_ARB0); GATE_ON(AHB_BRIDGE); GATE_ON(AHB_DATA_BUS); GATE_ON(AHB_CONTROL_BUS); }else{ GATE_OFF(AHB_ARB0); GATE_OFF(AHB_BRIDGE); GATE_OFF(AHB_DATA_BUS); GATE_OFF(AHB_CONTROL_BUS); } break; case MOD_DEMUX: PRINT_INFO("trun %s demux\n", flag? " on" : "off"); if(flag){ GATE_ON(DEMUX); }else{ GATE_OFF(DEMUX); } break; case MOD_SMART_CARD: PRINT_INFO("trun %s smart card\n", flag? " on" : "off"); if(flag){ GATE_ON(SMART_CARD_MPEG_DOMAIN); }else{ GATE_OFF(SMART_CARD_MPEG_DOMAIN); } break; case MOD_SDHC: PRINT_INFO("trun %s sdhc\n", flag? " on" : "off"); if(flag){ GATE_ON(SDHC); }else{ GATE_OFF(SDHC); } break; case MOD_STREAM: PRINT_INFO("trun %s stream\n", flag? " on" : "off"); if(flag){ GATE_ON(STREAM); }else{ GATE_OFF(STREAM); } break; case MOD_BLK_MOV: PRINT_INFO("trun %s blk_mov\n", flag? " on" : "off"); if(flag){ GATE_ON(BLK_MOV); }else{ GATE_OFF(BLK_MOV); } break; case MOD_MISC_DVIN: PRINT_INFO("trun %s dvin\n", flag? " on" : "off"); if(flag){ GATE_ON(MISC_DVIN); }else{ GATE_OFF(MISC_DVIN); } break; case MOD_MISC_RDMA: PRINT_INFO("trun %s rdma\n", flag? " on" : "off"); if(flag){ GATE_ON(MISC_RDMA); }else{ GATE_OFF(MISC_RDMA); } break; case MOD_USB0: PRINT_INFO("trun %s rdma\n", flag? " on" : "off"); if(flag){ GATE_ON(USB0); GATE_ON(MISC_USB0_TO_DDR); }else{ GATE_OFF(USB0); GATE_ON(MISC_USB0_TO_DDR); } break; case MOD_USB1: PRINT_INFO("trun %s rdma\n", flag? " on" : "off"); if(flag){ GATE_ON(USB1); GATE_ON(MISC_USB1_TO_DDR); }else{ GATE_OFF(USB1); GATE_ON(MISC_USB1_TO_DDR); } break; case MOD_SDIO: PRINT_INFO("trun %s rdma\n", flag? " on" : "off"); if(flag){ GATE_ON(SDIO); }else{ GATE_OFF(SDIO); } break; case MOD_VI_CORE: PRINT_INFO("trun %s vi core\n", flag? " on" : "off"); if(flag){ GATE_ON(VI_CORE); }else{ GATE_OFF(VI_CORE); } break; case MOD_LED_PWM: PRINT_INFO("trun %s led pwm\n", flag? " on" : "off"); if(flag){ GATE_ON(LED_PWM); }else{ GATE_OFF(LED_PWM); } break; case MOD_VDAC: printk("trun %s vdac\n", flag? " on" : "off"); if(flag){ #ifdef CONFIG_ARCH_MESON6 if( ((aml_read_reg32(P_VPU_VIU_VENC_MUX_CTRL)&0xf)==0x5) && (aml_read_reg32(P_ENCI_DACSEL_0)==0x1111) ) aml_write_reg32(P_VENC_VDAC_SETTING, 0x5);// 480cvbs/576cvbs mode else aml_write_reg32(P_VENC_VDAC_SETTING, 0x0); #else aml_write_reg32(P_VENC_VDAC_SETTING, 0x0); #endif }else{ aml_write_reg32(P_VENC_VDAC_SETTING, 0xffffffff); } break; default: PRINT_INFO("mod type not support\n"); ret = -1; break; } return ret; }
static int stmmac_probe_config_dt(struct platform_device *pdev, struct plat_stmmacenet_data *plat, const char **mac) { struct device_node *np = pdev->dev.of_node; struct stmmac_dma_cfg *dma_cfg; const struct of_device_id *device; #if defined (CONFIG_AML_NAND_KEY) || defined (CONFIG_SECURITYKEY) int ret; char *addr =NULL; #endif if (!np) return -ENODEV; device = of_match_device(stmmac_dt_ids, &pdev->dev); if (!device) return -ENODEV; if (device->data) { const struct stmmac_of_data *data = device->data; plat->has_gmac = data->has_gmac; plat->enh_desc = data->enh_desc; plat->tx_coe = data->tx_coe; plat->rx_coe = data->rx_coe; plat->bugged_jumbo = data->bugged_jumbo; plat->pmt = data->pmt; plat->riwt_off = data->riwt_off; plat->fix_mac_speed = data->fix_mac_speed; plat->bus_setup = data->bus_setup; plat->setup = data->setup; plat->free = data->free; plat->init = data->init; plat->exit = data->exit; } #if defined (CONFIG_AML_NAND_KEY) || defined (CONFIG_SECURITYKEY) ret = get_aml_key_kernel("mac", print_buff, 0); extenal_api_key_set_version("auto"); printk("ret = %d\nprint_buff=%s\n", ret, print_buff); if (ret >= 0) { strcpy(addr, print_buff); *mac = addr; } else { if(g_mac_addr_setup){ *mac = DEFMAC; } else{ *mac = of_get_mac_address(np); } } #else *mac = of_get_mac_address(np); #endif plat->interface = of_get_phy_mode(np); /* Get max speed of operation from device tree */ if (of_property_read_u32(np, "max-speed", &plat->max_speed)) plat->max_speed = -1; plat->bus_id = of_alias_get_id(np, "ethernet"); if (plat->bus_id < 0) plat->bus_id = 0; /* Default to phy auto-detection */ plat->phy_addr = -1; /* "snps,phy-addr" is not a standard property. Mark it as deprecated * and warn of its use. Remove this when phy node support is added. */ if (of_property_read_u32(np, "snps,phy-addr", &plat->phy_addr) == 0) dev_warn(&pdev->dev, "snps,phy-addr property is deprecated\n"); if (plat->phy_bus_name){ plat->mdio_bus_data = NULL; } else plat->mdio_bus_data = devm_kzalloc(&pdev->dev, sizeof(struct stmmac_mdio_bus_data), GFP_KERNEL); plat->force_sf_dma_mode = of_property_read_bool(np, "snps,force_sf_dma_mode"); /* Set the maxmtu to a default of JUMBO_LEN in case the * parameter is not present in the device tree. */ /* Set default value for multicast hash bins */ plat->multicast_filter_bins = HASH_TABLE_SIZE; /* Set default value for unicast filter entries */ plat->unicast_filter_entries = 1; /* * Currently only the properties needed on SPEAr600 * are provided. All other properties should be added * once needed on other platforms. */ #ifdef CONFIG_DWMAC_MESON #if 0 if(of_device_is_compatible(np,"amlogic,meson8m2-dwmac")){ aml_write_reg32(P_PERIPHS_PIN_MUX_6,0xffff); aml_write_reg32(P_PREG_ETH_REG0,0x7d21); aml_set_reg32_mask(P_HHI_MPLL_CNTL6,1<<27); aml_set_reg32_mask(P_HHI_GEN_CLK_CNTL,0xb803); aml_set_reg32_mask(P_HHI_MPLL_CNTL9,(1638<<0)| (0<<14)|(1<<15) | (1<<14) | (5<<16) | (0<<25) | (0<<26) |(0<<30) | (0<<31)); /* setup ethernet mode */ aml_clr_reg32_mask(P_HHI_MEM_PD_REG0, (1 << 3) | (1<<2)); /* hardware reset ethernet phy : gpioz14 connect phyreset pin*/ aml_clr_reg32_mask(P_PREG_PAD_GPIO2_EN_N, 1 << 28); aml_clr_reg32_mask(P_PREG_PAD_GPIO2_O, 1 << 28); mdelay(10); aml_set_reg32_mask(P_PREG_PAD_GPIO2_O, 1 << 28); } #endif #endif if (of_device_is_compatible(np, "st,spear600-gmac") || of_device_is_compatible(np, "snps,dwmac-3.70a") || of_device_is_compatible(np,"amlogic,meson8b-rgmii-dwmac")|| of_device_is_compatible(np,"amlogic,meson8m2-rgmii-dwmac")) { /* Note that the max-frame-size parameter as defined in the * ePAPR v1.1 spec is defined as max-frame-size, it's * actually used as the IEEE definition of MAC Client * data, or MTU. The ePAPR specification is confusing as * the definition is max-frame-size, but usage examples * are clearly MTUs */ of_property_read_u32(np, "max-frame-size", &plat->maxmtu); of_property_read_u32(np, "snps,multicast-filter-bins", &plat->multicast_filter_bins); of_property_read_u32(np, "snps,perfect-filter-entries", &plat->unicast_filter_entries); plat->unicast_filter_entries = dwmac1000_validate_ucast_entries( plat->unicast_filter_entries); plat->multicast_filter_bins = dwmac1000_validate_mcast_bins( plat->multicast_filter_bins); plat->has_gmac = 1; plat->pmt = 1; } if (of_device_is_compatible(np, "snps,dwmac-3.610") || of_device_is_compatible(np,"amlogic,meson6-dwmac")|| of_device_is_compatible(np, "snps,dwmac-3.710")) { plat->enh_desc = 1; plat->bugged_jumbo = 1; plat->force_sf_dma_mode = 1; } if (of_find_property(np, "snps,pbl", NULL)) { dma_cfg = devm_kzalloc(&pdev->dev, sizeof(*dma_cfg), GFP_KERNEL); if (!dma_cfg) return -ENOMEM; plat->dma_cfg = dma_cfg; of_property_read_u32(np, "snps,pbl", &dma_cfg->pbl); dma_cfg->fixed_burst = of_property_read_bool(np, "snps,fixed-burst"); dma_cfg->mixed_burst = of_property_read_bool(np, "snps,mixed-burst"); } plat->force_thresh_dma_mode = of_property_read_bool(np, "snps,force_thresh_dma_mode"); if (plat->force_thresh_dma_mode) { plat->force_sf_dma_mode = 0; pr_warn("force_sf_dma_mode is ignored if force_thresh_dma_mode is set."); } return 0; }
void clk_switch(int flag) { int i; if (flag) { for (i = CLK_COUNT - 1; i >= 0; i--) { if (clk_flag[i]) { if ((clks[i] == P_HHI_VID_CLK_CNTL)||(clks[i] == P_HHI_VIID_CLK_CNTL)) { aml_set_reg32_bits(clks[i],clk_flag[i],19,2); } else if (clks[i] == P_HHI_MPEG_CLK_CNTL) { if(uart_rate_backup == 0){ struct clk* sys_clk = clk_get_sys("clk81", NULL); sys_clk->rate = 0; uart_rate_backup = clk_get_rate(sys_clk); } wait_uart_empty(); aml_set_reg32_mask(clks[i],(1<<7));//gate on pll udelay(10); aml_set_reg32_mask(clks[i],(1<<8));//switch to pll udelay(10); aml_clr_reg32_mask(P_UART0_REG5, 0x7FFFFF); aml_set_reg32_bits(P_UART0_REG5, ((uart_rate_backup / (115200 * 4)) - 1) & 0x7fffff, 0, 23); aml_set_reg32_bits(P_UART0_REG5, 1, 23, 1); aml_clr_reg32_mask(P_UART1_REG5, 0x7FFFFF); aml_set_reg32_bits(P_UART1_REG5, ((uart_rate_backup / (115200 * 4)) - 1) & 0x7fffff, 0, 23); aml_set_reg32_bits(P_UART1_REG5, 1, 23, 1); aml_clr_reg32_mask(P_AO_UART2_REG5, 0x7FFFFF); aml_set_reg32_bits(P_AO_UART2_REG5, ((uart_rate_backup / (115200 * 4)) - 1) & 0x7fffff, 0, 23); aml_set_reg32_bits(P_AO_UART2_REG5, 1, 23, 1); aml_clr_reg32_mask(P_AO_UART_REG5, 0x7FFFFF); aml_set_reg32_bits(P_AO_UART_REG5, ((uart_rate_backup / (115200 * 4)) - 1) & 0x7fffff, 0, 23); aml_set_reg32_bits(P_AO_UART_REG5, 1, 23, 1); } else { aml_set_reg32_mask(clks[i],(1<<8)); } clk_flag[i] = 0; printk(KERN_INFO "clk %s(%x) on\n", clks_name[i], clks[i]); } #ifdef M6_TV_CLK_DEBUG if (clk_aud_23) aml_set_reg32_mask(P_HHI_AUD_CLK_CNTL,(1<<23)); if (clk_vdec_24) aml_set_reg32_mask(P_HHI_VDEC_CLK_CNTL,(1<<24)); #endif } } else { for (i = 0; i < CLK_COUNT; i++) { if ((clks[i] == P_HHI_VID_CLK_CNTL)||(clks[i] == P_HHI_VIID_CLK_CNTL)) { clk_flag[i] = aml_get_reg32_bits(clks[i], 19, 2); if (clk_flag[i]) { aml_clr_reg32_mask(clks[i], (1<<19)|(1<<20)); } } else if (clks[i] == P_HHI_MPEG_CLK_CNTL) { if (aml_read_reg32(clks[i]) & (1 << 8)) { if(xtal_uart_rate_backup == 0){//if no early suspend supported struct clk* sys_clk = clk_get_sys("xtal", NULL); xtal_uart_rate_backup = clk_get_rate(sys_clk); } wait_uart_empty(); clk_flag[i] = 1; aml_clr_reg32_mask(clks[i], (1 << 8)); // 24M udelay(10); aml_clr_reg32_mask(clks[i], (1 << 7)); // 24M udelay(10); aml_clr_reg32_mask(P_UART0_REG5, 0x7FFFFF); aml_set_reg32_bits(P_UART0_REG5, ((xtal_uart_rate_backup / (115200 * 4)) - 1) & 0x7fffff, 0, 23); aml_set_reg32_bits(P_UART0_REG5, 1, 23, 1); aml_clr_reg32_mask(P_UART1_REG5, 0x7FFFFF); aml_set_reg32_bits(P_UART1_REG5, ((xtal_uart_rate_backup / (115200 * 4)) - 1) & 0x7fffff, 0, 23); aml_set_reg32_bits(P_UART1_REG5, 1, 23, 1); aml_clr_reg32_mask(P_AO_UART2_REG5, 0x7FFFFF); aml_set_reg32_bits(P_AO_UART2_REG5, ((xtal_uart_rate_backup / (115200 * 4)) - 1) & 0x7fffff, 0, 23); aml_set_reg32_bits(P_AO_UART2_REG5, 1, 23, 1); aml_clr_reg32_mask(P_AO_UART_REG5, 0x7FFFFF); aml_set_reg32_bits(P_AO_UART_REG5, ((xtal_uart_rate_backup / (115200 * 4)) - 1) & 0x7fffff, 0, 23); aml_set_reg32_bits(P_AO_UART_REG5, 1, 23, 1); } } #ifdef M6_TV_CLK_DEBUG else if (clks[i] == P_HHI_AUD_CLK_CNTL) { clk_flag[i] = aml_get_reg32_bits(clks[i], 8, 1) ? 1 : 0; if (clk_flag[i]) { aml_clr_reg32_mask(clks[i], (1 << 8)); } clk_aud_23 = aml_get_reg32_bits(clks[i], 23, 1) ? 1 : 0; if (clk_aud_23) { aml_clr_reg32_mask(clks[i], (1 << 23)); } } else if (clks[i] == P_HHI_VDEC_CLK_CNTL) { clk_flag[i] = aml_get_reg32_bits(clks[i], 8, 1) ? 1 : 0; if (clk_flag[i]) { aml_clr_reg32_mask(clks[i], (1 << 8)); } clk_vdec_24 = aml_get_reg32_bits(clks[i], 24, 1) ? 1 : 0; if (clk_vdec_24) { aml_clr_reg32_mask(clks[i], (1 << 24)); } } else { clk_flag[i] = aml_get_reg32_bits(clks[i], 8, 1) ? 1 : 0; if (clk_flag[i]) { aml_clr_reg32_mask(clks[i], (1 << 8)); } } #else else { clk_flag[i] = aml_get_reg32_bits(clks[i], 8, 1) ? 1 : 0; if (clk_flag[i]) { aml_clr_reg32_mask(clks[i], (1 << 8)); } } #endif if (clk_flag[i]) { printk(KERN_INFO "clk %s(%x) off\n", clks_name[i], clks[i]); wait_uart_empty(); } } }