UINT8 *apple3_state::apple3_get_zpa_addr(offs_t offset)
{
m_zpa = (((offs_t) m_via_0_b) * 0x100) + offset;
if (m_via_0_b < 0x20)
return apple3_bankaddr(~0, m_zpa);
else if (m_via_0_b > 0x9F)
return apple3_bankaddr(~0, m_zpa - 0x8000);
else
return apple3_bankaddr(m_via_1_a, m_zpa - 0x2000);
}
static UINT8 *apple3_get_zpa_addr(offs_t offset)
{
zpa = (((offs_t) via_0_b) * 0x100) + offset;
if (via_0_b < 0x20)
return apple3_bankaddr(~0, zpa);
else if (via_0_b > 0x9F)
return apple3_bankaddr(~0, zpa - 0x8000);
else
return apple3_bankaddr(via_1_a, zpa - 0x2000);
}
static UINT8 *apple3_get_zpa_addr(running_machine &machine,offs_t offset)
{
apple3_state *state = machine.driver_data<apple3_state>();
state->m_zpa = (((offs_t) state->m_via_0_b) * 0x100) + offset;
if (state->m_via_0_b < 0x20)
return apple3_bankaddr(machine,~0, state->m_zpa);
else if (state->m_via_0_b > 0x9F)
return apple3_bankaddr(machine,~0, state->m_zpa - 0x8000);
else
return apple3_bankaddr(machine,state->m_via_1_a, state->m_zpa - 0x2000);
}
static void apple3_setbank(int mame_bank, UINT16 bank, offs_t offset)
{
UINT8 *ptr;
ptr = apple3_bankaddr(bank, offset);
memory_set_bankptr(mame_bank, ptr);
if (LOG_MEMORY)
{
logerror("\tbank #%d --> %02x/%04x [0x%08x]\n", mame_bank, (unsigned) bank, (unsigned) offset, ptr - mess_ram);
}
}
UINT8 *apple3_state::apple3_get_indexed_addr(offs_t offset)
{
UINT8 *result = nullptr;
// m_indir_bank is guaranteed to be between 0x80 and 0x8f
if (m_indir_bank == 0x8f)
{
/* get at that special ram under the VIAs */
if ((offset >= 0xFFD0) && (offset <= 0xFFEF))
result = apple3_bankaddr(~0, offset & 0x7FFF);
else if (offset < 0x2000)
result = apple3_bankaddr(~0, offset - 0x2000);
else if (offset > 0x9FFF)
result = apple3_bankaddr(~0, offset - 0x8000);
else
result = &m_ram->pointer()[offset - 0x2000];
}
else
{
result = apple3_bankaddr(m_indir_bank, offset);
}
return result;
}
static void apple3_setbank(running_machine &machine,const char *mame_bank, UINT16 bank, offs_t offset)
{
UINT8 *ptr;
apple3_state *state = machine.driver_data<apple3_state>();
ptr = apple3_bankaddr(machine,bank, offset);
state->membank(mame_bank)->set_base(ptr);
#if 0
if (LOG_MEMORY)
{
#ifdef PTR64
//logerror("\tbank %s --> %02x/%04x [0x%08lx]\n", mame_bank, (unsigned) bank, (unsigned)offset, ptr - machine.device<ram_device>(RAM_TAG)->pointer());
#else
logerror("\tbank %s --> %02x/%04x [0x%08lx]\n", mame_bank, (unsigned) bank, (unsigned)offset, ptr - machine.device<ram_device>(RAM_TAG)->pointer());
#endif
}
#endif
}
static UINT8 *apple3_get_indexed_addr(offs_t offset)
{
UINT8 n;
UINT8 *result = NULL;
if ((via_0_b >= 0x18) && (via_0_b <= 0x1F))
{
n = *apple3_bankaddr(~0, zpa ^ 0x0C00);
if (LOG_INDXADDR)
{
static UINT8 last_n;
if (last_n != n)
{
logerror("indxaddr: zpa=0x%04x n=0x%02x\n", zpa, n);
last_n = n;
}
}
if (n == 0x8F)
{
/* get at that special ram under the VIAs */
if ((offset >= 0xFFD0) && (offset <= 0xFFEF))
result = apple3_bankaddr(~0, offset & 0x7FFF);
else if (offset < 0x2000)
result = apple3_bankaddr(~0, offset - 0x2000);
else if (offset > 0x9FFF)
result = apple3_bankaddr(~0, offset - 0x8000);
else
result = &mess_ram[offset - 0x2000];
}
else if ((n >= 0x80) && (n <= 0x8E))
{
if (offset < 0x0100)
result = apple3_bankaddr(~0, ((offs_t) via_0_b) * 0x100 + offset);
else
result = apple3_bankaddr(n, offset);
}
else if (n == 0xFF)
{
if (offset < 0x2000)
result = apple3_bankaddr(~0, offset - 0x2000);
else if (offset < 0xA000)
result = apple3_bankaddr(via_1_a, offset - 0x2000);
else if (offset < 0xC000)
result = apple3_bankaddr(~0, offset - 0x8000);
else if (offset < 0xD000)
result = NULL;
else if (offset < 0xF000)
result = apple3_bankaddr(~0, offset - 0x8000);
else
result = (UINT8 *) ~0;
}
else if (offset < 0x0100)
{
result = apple3_bankaddr(~0, ((offs_t) via_0_b) * 0x100 + offset);
}
}
else if ((offset >= 0xF000) && (via_0_a & 0x01))
{
#if 0
/* The Apple /// Diagnostics seems to expect that indexed writes
* always write to RAM. That image jumps to an address that is
* undefined unless this code is enabled. However, the Sara
* emulator does not have corresponding code here, though Chris
* Smolinski does not rule out the possibility
*/
result = apple3_bankaddr(~0, offset - 0x8000);
#endif
}
return result;
}
void apple3_state::apple3_update_memory()
{
UINT16 bank;
UINT8 page;
if (LOG_MEMORY)
{
logerror("apple3_update_memory(): via_0_b=0x%02x via_1_a=0x0x%02x\n", m_via_0_b, m_via_1_a);
}
machine().device("maincpu")->set_unscaled_clock((m_via_0_a & ENV_SLOWSPEED) ? 1021800 : 2000000);
/* bank 2 (0100-01FF) */
if (!(m_via_0_a & ENV_STACK1XX))
{
if (m_via_0_b < 0x20)
{
bank = ~0; /* system bank */
page = m_via_0_b ^ 0x01;
}
else if (m_via_0_b >= 0xA0)
{
bank = ~0; /* system bank */
page = (m_via_0_b ^ 0x01) - 0x80;
}
else
{
bank = m_via_1_a;
page = (m_via_0_b ^ 0x01) - 0x20;
}
}
else
{
bank = ~0;
page = 0x01;
}
m_bank2 = apple3_bankaddr(bank, ((offs_t) page) * 0x100);
/* bank 3 (0200-1FFF) */
m_bank3 = apple3_bankaddr(~0, 0x0200);
/* bank 4 (2000-9FFF) */
m_bank4 = apple3_bankaddr(m_via_1_a, 0x0000);
/* bank 5 (A000-BFFF) */
m_bank5 = apple3_bankaddr(~0, 0x2000);
/* bank 8 (C000-C0FF) */
if (!(m_via_0_a & ENV_IOENABLE))
{
m_bank8 = apple3_bankaddr(~0, 0x4000);
}
/* bank 9 (C100-C4FF) */
if (!(m_via_0_a & ENV_IOENABLE))
{
m_bank9 = apple3_bankaddr(~0, 0x4100);
}
/* bank 10 (C500-C7FF) */
m_bank10 = apple3_bankaddr(~0, 0x4500);
/* bank 11 (C800-CFFF) */
if (!(m_via_0_a & ENV_IOENABLE))
{
m_bank11 = apple3_bankaddr(~0, 0x4800);
}
/* install bank 6 (D000-EFFF) */
m_bank6 = apple3_bankaddr(~0, 0x5000);
/* install bank 7 (F000-FFFF) */
m_bank7wr = apple3_bankaddr(~0, 0x7000);
if (m_via_0_a & ENV_ROMENABLE)
{
m_bank7rd = memregion("maincpu")->base();
}
else
{
m_bank7rd = m_bank7wr;
// if we had an IRQ waiting for RAM to be paged in...
apple3_irq_update();
}
}
