static void ar71xx_misc_irq_dispatch(void) { u32 pending; pending = ar71xx_reset_rr(RESET_REG_MISC_INT_STATUS) & ar71xx_reset_rr(RESET_REG_MISC_INT_ENABLE); if (pending & MISC_INT_UART) do_IRQ(AR71XX_MISC_IRQ_UART); else if (pending & MISC_INT_DMA) do_IRQ(AR71XX_MISC_IRQ_DMA); else if (pending & MISC_INT_PERFC) do_IRQ(AR71XX_MISC_IRQ_PERFC); else if (pending & MISC_INT_TIMER) do_IRQ(AR71XX_MISC_IRQ_TIMER); else if (pending & MISC_INT_OHCI) do_IRQ(AR71XX_MISC_IRQ_OHCI); else if (pending & MISC_INT_ERROR) do_IRQ(AR71XX_MISC_IRQ_ERROR); else if (pending & MISC_INT_GPIO) ar71xx_gpio_irq_dispatch(); else if (pending & MISC_INT_WDOG) do_IRQ(AR71XX_MISC_IRQ_WDOG); else spurious_interrupt(); }
int ar71xx_device_stopped(u32 mask) { unsigned long flags; u32 t; switch (ar71xx_soc) { case AR71XX_SOC_AR7130: case AR71XX_SOC_AR7141: case AR71XX_SOC_AR7161: local_irq_save(flags); t = ar71xx_reset_rr(AR71XX_RESET_REG_RESET_MODULE); local_irq_restore(flags); break; case AR71XX_SOC_AR7240: local_irq_save(flags); t = ar71xx_reset_rr(AR724X_RESET_REG_RESET_MODULE); local_irq_restore(flags); break; case AR71XX_SOC_AR9130: case AR71XX_SOC_AR9132: local_irq_save(flags); t = ar71xx_reset_rr(AR91XX_RESET_REG_RESET_MODULE); local_irq_restore(flags); break; default: BUG(); } return ((t & mask) == mask); }
static void ar71xx_pci_irq_dispatch(void) { u32 pending; pending = ar71xx_reset_rr(RESET_REG_PCI_INT_STATUS) & ar71xx_reset_rr(RESET_REG_PCI_INT_ENABLE); if (pending & PCI_INT_DEV0) do_IRQ(AR71XX_PCI_IRQ_DEV0); else if (pending & PCI_INT_DEV1) do_IRQ(AR71XX_PCI_IRQ_DEV1); else if (pending & PCI_INT_DEV2) do_IRQ(AR71XX_PCI_IRQ_DEV2); else spurious_interrupt(); }
void ar71xx_device_start(u32 mask) { unsigned long flags; u32 mask_inv; u32 t; switch (ar71xx_soc) { case AR71XX_SOC_AR7130: case AR71XX_SOC_AR7141: case AR71XX_SOC_AR7161: local_irq_save(flags); t = ar71xx_reset_rr(AR71XX_RESET_REG_RESET_MODULE); ar71xx_reset_wr(AR71XX_RESET_REG_RESET_MODULE, t & ~mask); local_irq_restore(flags); break; case AR71XX_SOC_AR7240: mask_inv = mask & RESET_MODULE_USB_OHCI_DLL_7240; local_irq_save(flags); t = ar71xx_reset_rr(AR724X_RESET_REG_RESET_MODULE); t &= ~mask; t |= mask_inv; ar71xx_reset_wr(AR724X_RESET_REG_RESET_MODULE, t); local_irq_restore(flags); break; case AR71XX_SOC_AR9130: case AR71XX_SOC_AR9132: local_irq_save(flags); t = ar71xx_reset_rr(AR91XX_RESET_REG_RESET_MODULE); ar71xx_reset_wr(AR91XX_RESET_REG_RESET_MODULE, t & ~mask); local_irq_restore(flags); break; default: BUG(); } }
static void qca956x_wmac_init(void) { u32 t; ar9xxx_wmac_device.name = "qca956x_wmac"; ar9xxx_wmac_resources[0].start = QCA956X_WMAC_BASE; ar9xxx_wmac_resources[0].end = QCA956X_WMAC_BASE + QCA956X_WMAC_SIZE - 1; ar9xxx_wmac_resources[1].start = AR934X_IP2_IRQ(1); ar9xxx_wmac_resources[1].end = AR934X_IP2_IRQ(1); t = ar71xx_reset_rr(QCA956X_RESET_REG_BOOTSTRAP); if (t & QCA956X_BOOTSTRAP_REF_CLK_40) ar9xxx_wmac_data.is_clk_25mhz = false; else ar9xxx_wmac_data.is_clk_25mhz = true; }
static void qca953x_wmac_init(void) { u32 t; ar9xxx_wmac_device.name = "qca953x_wmac"; ar9xxx_wmac_resources[0].start = QCA953X_WMAC_BASE; ar9xxx_wmac_resources[0].end = QCA953X_WMAC_BASE + QCA953X_WMAC_SIZE - 1; ar9xxx_wmac_resources[1].start = AR71XX_CPU_IRQ_IP2; ar9xxx_wmac_resources[1].end = AR71XX_CPU_IRQ_IP2; t = ar71xx_reset_rr(QCA953X_RESET_REG_BOOTSTRAP); if (t & QCA953X_BOOTSTRAP_REF_CLK_40) ar9xxx_wmac_data.is_clk_25mhz = false; else ar9xxx_wmac_data.is_clk_25mhz = true; ar9xxx_wmac_data.get_mac_revision = ar93xx_get_wmac_revision; }
static int __devinit ar71xx_wdt_probe(struct platform_device *pdev) { int ret; max_timeout = (0xfffffffful / ar71xx_ahb_freq); wdt_timeout = (max_timeout < WDT_TIMEOUT) ? max_timeout : WDT_TIMEOUT; if (ar71xx_reset_rr(AR71XX_RESET_REG_WDOG_CTRL) & WDOG_CTRL_LAST_RESET) boot_status = WDIOF_CARDRESET; ret = misc_register(&ar71xx_wdt_miscdev); if (ret) goto err_out; printk(KERN_INFO DRV_DESC " version " DRV_VERSION "\n"); printk(KERN_DEBUG DRV_NAME ": timeout=%d secs (max=%d)\n", wdt_timeout, max_timeout); return 0; err_out: return ret; }
static int ar933x_wmac_reset(void) { unsigned retries = 0; ar71xx_device_stop(AR933X_RESET_WMAC); ar71xx_device_start(AR933X_RESET_WMAC); while (1) { u32 bootstrap; bootstrap = ar71xx_reset_rr(AR933X_RESET_REG_BOOTSTRAP); if ((bootstrap & AR933X_BOOTSTRAP_EEPBUSY) == 0) return 0; if (retries > 20) break; udelay(10000); retries++; } printk(KERN_EMERG "ar93xx: WMAC reset timed out"); return -ETIMEDOUT; }
static void ar71xx_pci_irq_mask(unsigned int irq) { irq -= AR71XX_PCI_IRQ_BASE; ar71xx_reset_wr(RESET_REG_PCI_INT_ENABLE, ar71xx_reset_rr(RESET_REG_PCI_INT_ENABLE) & ~(1 << irq)); }
static void ar71xx_misc_irq_unmask(unsigned int irq) { irq -= AR71XX_MISC_IRQ_BASE; ar71xx_reset_wr(RESET_REG_MISC_INT_ENABLE, ar71xx_reset_rr(RESET_REG_MISC_INT_ENABLE) | (1 << irq)); }