static int show_cpuinfo(struct seq_file *m, void *v) { char *str; int cpu_id = ptr_to_cpu(v); if (!cpu_online(cpu_id)) { seq_printf(m, "processor [%d]\t: Offline\n", cpu_id); goto done; } str = (char *)__get_free_page(GFP_TEMPORARY); if (!str) goto done; seq_printf(m, arc_cpu_mumbojumbo(cpu_id, str, PAGE_SIZE)); seq_printf(m, "Bogo MIPS\t: %lu.%02lu\n", loops_per_jiffy / (500000 / HZ), (loops_per_jiffy / (5000 / HZ)) % 100); seq_printf(m, arc_mmu_mumbojumbo(cpu_id, str, PAGE_SIZE)); seq_printf(m, arc_cache_mumbojumbo(cpu_id, str, PAGE_SIZE)); seq_printf(m, arc_extn_mumbojumbo(cpu_id, str, PAGE_SIZE)); seq_printf(m, arc_platform_smp_cpuinfo()); free_page((unsigned long)str); done: seq_printf(m, "\n"); return 0; }
static int show_cpuinfo(struct seq_file *m, void *v) { char *str; int cpu_id = ptr_to_cpu(v); str = (char *)__get_free_page(GFP_TEMPORARY); if (!str) goto done; seq_printf(m, arc_cpu_mumbojumbo(cpu_id, str, PAGE_SIZE)); seq_printf(m, "Bogo MIPS : \t%lu.%02lu\n", loops_per_jiffy / (500000 / HZ), (loops_per_jiffy / (5000 / HZ)) % 100); seq_printf(m, arc_mmu_mumbojumbo(cpu_id, str, PAGE_SIZE)); seq_printf(m, arc_cache_mumbojumbo(cpu_id, str, PAGE_SIZE)); seq_printf(m, arc_extn_mumbojumbo(cpu_id, str, PAGE_SIZE)); #ifdef CONFIG_SMP seq_printf(m, arc_platform_smp_cpuinfo()); #endif free_page((unsigned long)str); done: seq_printf(m, "\n\n"); return 0; }
void arc_cache_init(void) { unsigned int __maybe_unused cpu = smp_processor_id(); char str[256]; printk(arc_cache_mumbojumbo(0, str, sizeof(str))); if (IS_ENABLED(CONFIG_ARC_HAS_ICACHE)) { struct cpuinfo_arc_cache *ic = &cpuinfo_arc700[cpu].icache; if (!ic->ver) panic("cache support enabled but non-existent cache\n"); if (ic->line_len != L1_CACHE_BYTES) panic("ICache line [%d] != kernel Config [%d]", ic->line_len, L1_CACHE_BYTES); if (ic->ver != CONFIG_ARC_MMU_VER) panic("Cache ver [%d] doesn't match MMU ver [%d]\n", ic->ver, CONFIG_ARC_MMU_VER); /* * In MMU v4 (HS38x) the alising icache config uses IVIL/PTAG * pair to provide vaddr/paddr respectively, just as in MMU v3 */ if (is_isa_arcv2() && ic->alias) _cache_line_loop_ic_fn = __cache_line_loop_v3; else _cache_line_loop_ic_fn = __cache_line_loop; } if (IS_ENABLED(CONFIG_ARC_HAS_DCACHE)) { struct cpuinfo_arc_cache *dc = &cpuinfo_arc700[cpu].dcache; if (!dc->ver) panic("cache support enabled but non-existent cache\n"); if (dc->line_len != L1_CACHE_BYTES) panic("DCache line [%d] != kernel Config [%d]", dc->line_len, L1_CACHE_BYTES); /* check for D-Cache aliasing on ARCompact: ARCv2 has PIPT */ if (is_isa_arcompact()) { int handled = IS_ENABLED(CONFIG_ARC_CACHE_VIPT_ALIASING); if (dc->alias && !handled) panic("Enable CONFIG_ARC_CACHE_VIPT_ALIASING\n"); else if (!dc->alias && handled) panic("Disable CONFIG_ARC_CACHE_VIPT_ALIASING\n"); } } }
static int show_cpuinfo(struct seq_file *m, void *v) { char *str; int cpu_id = ptr_to_cpu(v); struct device *cpu_dev = get_cpu_device(cpu_id); struct clk *cpu_clk; unsigned long freq = 0; if (!cpu_online(cpu_id)) { seq_printf(m, "processor [%d]\t: Offline\n", cpu_id); goto done; } str = (char *)__get_free_page(GFP_KERNEL); if (!str) goto done; seq_printf(m, arc_cpu_mumbojumbo(cpu_id, str, PAGE_SIZE)); cpu_clk = clk_get(cpu_dev, NULL); if (IS_ERR(cpu_clk)) { seq_printf(m, "CPU speed \t: Cannot get clock for processor [%d]\n", cpu_id); } else { freq = clk_get_rate(cpu_clk); } if (freq) seq_printf(m, "CPU speed\t: %lu.%02lu Mhz\n", freq / 1000000, (freq / 10000) % 100); seq_printf(m, "Bogo MIPS\t: %lu.%02lu\n", loops_per_jiffy / (500000 / HZ), (loops_per_jiffy / (5000 / HZ)) % 100); seq_printf(m, arc_mmu_mumbojumbo(cpu_id, str, PAGE_SIZE)); seq_printf(m, arc_cache_mumbojumbo(cpu_id, str, PAGE_SIZE)); seq_printf(m, arc_extn_mumbojumbo(cpu_id, str, PAGE_SIZE)); seq_printf(m, arc_platform_smp_cpuinfo()); free_page((unsigned long)str); done: seq_printf(m, "\n"); return 0; }
/* * 1. Validate the Cache Geomtery (compile time config matches hardware) * 2. If I-cache suffers from aliasing, setup work arounds (difft flush rtn) * (aliasing D-cache configurations are not supported YET) * 3. Enable the Caches, setup default flush mode for D-Cache * 3. Calculate the SHMLBA used by user space */ void arc_cache_init(void) { unsigned int __maybe_unused cpu = smp_processor_id(); char str[256]; printk(arc_cache_mumbojumbo(0, str, sizeof(str))); if (IS_ENABLED(CONFIG_ARC_HAS_ICACHE)) { struct cpuinfo_arc_cache *ic = &cpuinfo_arc700[cpu].icache; if (!ic->ver) panic("cache support enabled but non-existent cache\n"); if (ic->line_len != L1_CACHE_BYTES) panic("ICache line [%d] != kernel Config [%d]", ic->line_len, L1_CACHE_BYTES); if (ic->ver != CONFIG_ARC_MMU_VER) panic("Cache ver [%d] doesn't match MMU ver [%d]\n", ic->ver, CONFIG_ARC_MMU_VER); } if (IS_ENABLED(CONFIG_ARC_HAS_DCACHE)) { struct cpuinfo_arc_cache *dc = &cpuinfo_arc700[cpu].dcache; int handled; if (!dc->ver) panic("cache support enabled but non-existent cache\n"); if (dc->line_len != L1_CACHE_BYTES) panic("DCache line [%d] != kernel Config [%d]", dc->line_len, L1_CACHE_BYTES); /* check for D-Cache aliasing */ handled = IS_ENABLED(CONFIG_ARC_CACHE_VIPT_ALIASING); if (dc->alias && !handled) panic("Enable CONFIG_ARC_CACHE_VIPT_ALIASING\n"); else if (!dc->alias && handled) panic("Don't need CONFIG_ARC_CACHE_VIPT_ALIASING\n"); } }
/* * 1. Validate the Cache Geomtery (compile time config matches hardware) * 2. If I-cache suffers from aliasing, setup work arounds (difft flush rtn) * (aliasing D-cache configurations are not supported YET) * 3. Enable the Caches, setup default flush mode for D-Cache * 3. Calculate the SHMLBA used by user space */ void arc_cache_init(void) { unsigned int __maybe_unused cpu = smp_processor_id(); struct cpuinfo_arc_cache __maybe_unused *ic, __maybe_unused *dc; char str[256]; printk(arc_cache_mumbojumbo(0, str, sizeof(str))); #ifdef CONFIG_ARC_HAS_ICACHE ic = &cpuinfo_arc700[cpu].icache; if (ic->ver) { if (ic->line_len != L1_CACHE_BYTES) panic("ICache line [%d] != kernel Config [%d]", ic->line_len, L1_CACHE_BYTES); if (ic->ver != CONFIG_ARC_MMU_VER) panic("Cache ver [%d] doesn't match MMU ver [%d]\n", ic->ver, CONFIG_ARC_MMU_VER); } #endif #ifdef CONFIG_ARC_HAS_DCACHE dc = &cpuinfo_arc700[cpu].dcache; if (dc->ver) { unsigned int dcache_does_alias; if (dc->line_len != L1_CACHE_BYTES) panic("DCache line [%d] != kernel Config [%d]", dc->line_len, L1_CACHE_BYTES); /* check for D-Cache aliasing */ dcache_does_alias = (dc->sz / dc->assoc) > PAGE_SIZE; if (dcache_does_alias && !cache_is_vipt_aliasing()) panic("Enable CONFIG_ARC_CACHE_VIPT_ALIASING\n"); else if (!dcache_does_alias && cache_is_vipt_aliasing()) panic("Don't need CONFIG_ARC_CACHE_VIPT_ALIASING\n"); } #endif }
static int show_cpuinfo(struct seq_file *m, void *v) { char *str; int cpu_id = ptr_to_cpu(v); struct device_node *core_clk = of_find_node_by_name(NULL, "core_clk"); u32 freq = 0; if (!cpu_online(cpu_id)) { seq_printf(m, "processor [%d]\t: Offline\n", cpu_id); goto done; } str = (char *)__get_free_page(GFP_TEMPORARY); if (!str) goto done; seq_printf(m, arc_cpu_mumbojumbo(cpu_id, str, PAGE_SIZE)); of_property_read_u32(core_clk, "clock-frequency", &freq); if (freq) seq_printf(m, "CPU speed\t: %u.%02u Mhz\n", freq / 1000000, (freq / 10000) % 100); seq_printf(m, "Bogo MIPS\t: %lu.%02lu\n", loops_per_jiffy / (500000 / HZ), (loops_per_jiffy / (5000 / HZ)) % 100); seq_printf(m, arc_mmu_mumbojumbo(cpu_id, str, PAGE_SIZE)); seq_printf(m, arc_cache_mumbojumbo(cpu_id, str, PAGE_SIZE)); seq_printf(m, arc_extn_mumbojumbo(cpu_id, str, PAGE_SIZE)); seq_printf(m, arc_platform_smp_cpuinfo()); free_page((unsigned long)str); done: seq_printf(m, "\n"); return 0; }
/* * 1. Validate the Cache Geomtery (compile time config matches hardware) * 2. If I-cache suffers from aliasing, setup work arounds (difft flush rtn) * (aliasing D-cache configurations are not supported YET) * 3. Enable the Caches, setup default flush mode for D-Cache * 3. Calculate the SHMLBA used by user space */ void arc_cache_init(void) { unsigned int cpu = smp_processor_id(); struct cpuinfo_arc_cache *ic = &cpuinfo_arc700[cpu].icache; struct cpuinfo_arc_cache *dc = &cpuinfo_arc700[cpu].dcache; unsigned int dcache_does_alias, temp; char str[256]; printk(arc_cache_mumbojumbo(0, str, sizeof(str))); if (!ic->ver) goto chk_dc; #ifdef CONFIG_ARC_HAS_ICACHE /* 1. Confirm some of I-cache params which Linux assumes */ if (ic->line_len != ARC_ICACHE_LINE_LEN) panic("Cache H/W doesn't match kernel Config"); if (ic->ver != CONFIG_ARC_MMU_VER) panic("Cache ver doesn't match MMU ver\n"); #endif /* Enable/disable I-Cache */ temp = read_aux_reg(ARC_REG_IC_CTRL); #ifdef CONFIG_ARC_HAS_ICACHE temp &= ~IC_CTRL_CACHE_DISABLE; #else temp |= IC_CTRL_CACHE_DISABLE; #endif write_aux_reg(ARC_REG_IC_CTRL, temp); chk_dc: if (!dc->ver) return; #ifdef CONFIG_ARC_HAS_DCACHE if (dc->line_len != ARC_DCACHE_LINE_LEN) panic("Cache H/W doesn't match kernel Config"); /* check for D-Cache aliasing */ dcache_does_alias = (dc->sz / dc->assoc) > PAGE_SIZE; if (dcache_does_alias && !cache_is_vipt_aliasing()) panic("Enable CONFIG_ARC_CACHE_VIPT_ALIASING\n"); else if (!dcache_does_alias && cache_is_vipt_aliasing()) panic("Don't need CONFIG_ARC_CACHE_VIPT_ALIASING\n"); #endif /* Set the default Invalidate Mode to "simpy discard dirty lines" * as this is more frequent then flush before invalidate * Ofcourse we toggle this default behviour when desired */ temp = read_aux_reg(ARC_REG_DC_CTRL); temp &= ~DC_CTRL_INV_MODE_FLUSH; #ifdef CONFIG_ARC_HAS_DCACHE /* Enable D-Cache: Clear Bit 0 */ write_aux_reg(ARC_REG_DC_CTRL, temp & ~IC_CTRL_CACHE_DISABLE); #else /* Flush D cache */ write_aux_reg(ARC_REG_DC_FLSH, 0x1); /* Disable D cache */ write_aux_reg(ARC_REG_DC_CTRL, temp | IC_CTRL_CACHE_DISABLE); #endif return; }