/**
* arc_emac_adjust_link - Adjust the PHY link duplex.
* @ndev: Pointer to the net_device structure.
*
* This function is called to change the duplex setting after auto negotiation
* is done by the PHY.
*/
static void arc_emac_adjust_link(struct net_device *ndev)
{
struct arc_emac_priv *priv = netdev_priv(ndev);
struct phy_device *phy_dev = ndev->phydev;
unsigned int reg, state_changed = 0;
if (priv->link != phy_dev->link) {
priv->link = phy_dev->link;
state_changed = 1;
}
if (priv->speed != phy_dev->speed) {
priv->speed = phy_dev->speed;
state_changed = 1;
if (priv->set_mac_speed)
priv->set_mac_speed(priv, priv->speed);
}
if (priv->duplex != phy_dev->duplex) {
reg = arc_reg_get(priv, R_CTRL);
if (phy_dev->duplex == DUPLEX_FULL)
reg |= ENFL_MASK;
else
reg &= ~ENFL_MASK;
arc_reg_set(priv, R_CTRL, reg);
priv->duplex = phy_dev->duplex;
state_changed = 1;
}
if (state_changed)
phy_print_status(phy_dev);
}
/**
* arc_emac_rx_miss_handle - handle R_MISS register
* @ndev: Pointer to the net_device structure.
*/
static void arc_emac_rx_miss_handle(struct net_device *ndev)
{
struct arc_emac_priv *priv = netdev_priv(ndev);
struct net_device_stats *stats = &ndev->stats;
unsigned int miss;
miss = arc_reg_get(priv, R_MISS);
if (miss) {
stats->rx_errors += miss;
stats->rx_missed_errors += miss;
priv->rx_missed_errors += miss;
}
}
/**
* arc_emac_intr - Global interrupt handler for EMAC.
* @irq: irq number.
* @dev_instance: device instance.
*
* returns: IRQ_HANDLED for all cases.
*
* ARC EMAC has only 1 interrupt line, and depending on bits raised in
* STATUS register we may tell what is a reason for interrupt to fire.
*/
static irqreturn_t arc_emac_intr(int irq, void *dev_instance)
{
struct net_device *ndev = dev_instance;
struct arc_emac_priv *priv = netdev_priv(ndev);
struct net_device_stats *stats = &ndev->stats;
unsigned int status;
status = arc_reg_get(priv, R_STATUS);
status &= ~MDIO_MASK;
/* Reset all flags except "MDIO complete" */
arc_reg_set(priv, R_STATUS, status);
if (status & (RXINT_MASK | TXINT_MASK)) {
if (likely(napi_schedule_prep(&priv->napi))) {
arc_reg_clr(priv, R_ENABLE, RXINT_MASK | TXINT_MASK);
__napi_schedule(&priv->napi);
}
}
if (status & ERR_MASK) {
/* MSER/RXCR/RXFR/RXFL interrupt fires on corresponding
* 8-bit error counter overrun.
*/
if (status & MSER_MASK) {
stats->rx_missed_errors += 0x100;
stats->rx_errors += 0x100;
priv->rx_missed_errors += 0x100;
napi_schedule(&priv->napi);
}
if (status & RXCR_MASK) {
stats->rx_crc_errors += 0x100;
stats->rx_errors += 0x100;
}
if (status & RXFR_MASK) {
stats->rx_frame_errors += 0x100;
stats->rx_errors += 0x100;
}
if (status & RXFL_MASK) {
stats->rx_over_errors += 0x100;
stats->rx_errors += 0x100;
}
}
return IRQ_HANDLED;
}
static int arc_emac_mdio_read(struct mii_bus *bus, int phy_addr, int reg_num)
{
struct arc_emac_priv *priv = bus->priv;
int error;
arc_reg_set(priv, R_MDIO,
0x60020000 | (phy_addr << 23) | (reg_num << 18));
error = arc_mdio_complete_wait(priv);
if (error < 0)
return error;
return arc_reg_get(priv, R_MDIO) & 0xffff;
}
static int arc_mdio_complete_wait(struct arc_emac_priv *priv)
{
uint64_t start = get_time_ns();
while (!is_timeout(start, 1000 * MSECOND)) {
if (arc_reg_get(priv, R_STATUS) & MDIO_MASK) {
/* Reset "MDIO complete" flag */
arc_reg_set(priv, R_STATUS, MDIO_MASK);
return 0;
}
}
return -ETIMEDOUT;
}
/**
* arc_emac_stats - Get system network statistics.
* @ndev: Pointer to net_device structure.
*
* Returns the address of the device statistics structure.
* Statistics are updated in interrupt handler.
*/
static struct net_device_stats *arc_emac_stats(struct net_device *ndev)
{
struct arc_emac_priv *priv = netdev_priv(ndev);
struct net_device_stats *stats = &priv->stats;
unsigned long miss, rxerr;
u8 rxcrc, rxfram, rxoflow;
rxerr = arc_reg_get(priv, R_RXERR);
miss = arc_reg_get(priv, R_MISS);
rxcrc = rxerr;
rxfram = rxerr >> 8;
rxoflow = rxerr >> 16;
stats->rx_errors += miss;
stats->rx_errors += rxcrc + rxfram + rxoflow;
stats->rx_over_errors += rxoflow;
stats->rx_frame_errors += rxfram;
stats->rx_crc_errors += rxcrc;
stats->rx_missed_errors += miss;
return stats;
}
/**
* arc_mdio_read - MDIO interface read function.
* @bus: Pointer to MII bus structure.
* @phy_addr: Address of the PHY device.
* @reg_num: PHY register to read.
*
* returns: The register contents on success, -ETIMEDOUT on a timeout.
*
* Reads the contents of the requested register from the requested PHY
* address.
*/
static int arc_mdio_read(struct mii_bus *bus, int phy_addr, int reg_num)
{
struct arc_emac_priv *priv = bus->priv;
unsigned int value;
int error;
arc_reg_set(priv, R_MDIO,
0x60020000 | (phy_addr << 23) | (reg_num << 18));
error = arc_mdio_complete_wait(priv);
if (error < 0)
return error;
value = arc_reg_get(priv, R_MDIO) & 0xffff;
dev_dbg(priv->dev, "arc_mdio_read(phy_addr=%i, reg_num=%x) = %x\n",
phy_addr, reg_num, value);
return value;
}
/**
* arc_mdio_complete_wait - Waits until MDIO transaction is completed.
* @priv: Pointer to ARC EMAC private data structure.
*
* returns: 0 on success, -ETIMEDOUT on a timeout.
*/
static int arc_mdio_complete_wait(struct arc_emac_priv *priv)
{
unsigned int i;
for (i = 0; i < ARC_MDIO_COMPLETE_POLL_COUNT * 40; i++) {
unsigned int status = arc_reg_get(priv, R_STATUS);
status &= MDIO_MASK;
if (status) {
/* Reset "MDIO complete" flag */
arc_reg_set(priv, R_STATUS, status);
return 0;
}
msleep(25);
}
return -ETIMEDOUT;
}
static int arc_emac_send(struct eth_device *edev, void *data, int length)
{
struct arc_emac_priv *priv = edev->priv;
struct arc_emac_bd *bd = &priv->txbd[priv->txbd_curr];
char txbuf[EMAC_ZLEN];
int ret;
/* Pad short frames to minimum length */
if (length < EMAC_ZLEN) {
memcpy(txbuf, data, length);
memset(txbuf + length, 0, EMAC_ZLEN - length);
data = txbuf;
length = EMAC_ZLEN;
}
dma_flush_range((unsigned long)data, (unsigned long)data + length);
bd->data = cpu_to_le32(data);
bd->info = cpu_to_le32(FOR_EMAC | FIRST_OR_LAST_MASK | length);
arc_reg_set(priv, R_STATUS, TXPL_MASK);
ret = wait_on_timeout(20 * MSECOND,
(arc_reg_get(priv, R_STATUS) & TXINT_MASK) != 0);
if (ret) {
dev_err(&edev->dev, "transmit timeout\n");
return ret;
}
arc_reg_set(priv, R_STATUS, TXINT_MASK);
priv->txbd_curr++;
priv->txbd_curr %= TX_BD_NUM;
return 0;
}
static int arc_emac_probe(struct platform_device *pdev)
{
struct resource res_regs;
struct device_node *phy_node;
struct arc_emac_priv *priv;
struct net_device *ndev;
const char *mac_addr;
unsigned int id, clock_frequency, irq;
int err;
if (!pdev->dev.of_node)
return -ENODEV;
/* Get PHY from device tree */
phy_node = of_parse_phandle(pdev->dev.of_node, "phy", 0);
if (!phy_node) {
dev_err(&pdev->dev, "failed to retrieve phy description from device tree\n");
return -ENODEV;
}
/* Get EMAC registers base address from device tree */
err = of_address_to_resource(pdev->dev.of_node, 0, &res_regs);
if (err) {
dev_err(&pdev->dev, "failed to retrieve registers base from device tree\n");
return -ENODEV;
}
/* Get CPU clock frequency from device tree */
if (of_property_read_u32(pdev->dev.of_node, "clock-frequency",
&clock_frequency)) {
dev_err(&pdev->dev, "failed to retrieve <clock-frequency> from device tree\n");
return -EINVAL;
}
/* Get IRQ from device tree */
irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
if (!irq) {
dev_err(&pdev->dev, "failed to retrieve <irq> value from device tree\n");
return -ENODEV;
}
ndev = alloc_etherdev(sizeof(struct arc_emac_priv));
if (!ndev)
return -ENOMEM;
platform_set_drvdata(pdev, ndev);
SET_NETDEV_DEV(ndev, &pdev->dev);
ndev->netdev_ops = &arc_emac_netdev_ops;
ndev->ethtool_ops = &arc_emac_ethtool_ops;
ndev->watchdog_timeo = TX_TIMEOUT;
/* FIXME :: no multicast support yet */
ndev->flags &= ~IFF_MULTICAST;
priv = netdev_priv(ndev);
priv->dev = &pdev->dev;
priv->ndev = ndev;
priv->regs = devm_ioremap_resource(&pdev->dev, &res_regs);
if (IS_ERR(priv->regs)) {
err = PTR_ERR(priv->regs);
goto out;
}
dev_dbg(&pdev->dev, "Registers base address is 0x%p\n", priv->regs);
id = arc_reg_get(priv, R_ID);
/* Check for EMAC revision 5 or 7, magic number */
if (!(id == 0x0005fd02 || id == 0x0007fd02)) {
dev_err(&pdev->dev, "ARC EMAC not detected, id=0x%x\n", id);
err = -ENODEV;
goto out;
}
dev_info(&pdev->dev, "ARC EMAC detected with id: 0x%x\n", id);
/* Set poll rate so that it polls every 1 ms */
arc_reg_set(priv, R_POLLRATE, clock_frequency / 1000000);
/* Get max speed of operation from device tree */
if (of_property_read_u32(pdev->dev.of_node, "max-speed",
&priv->max_speed)) {
dev_err(&pdev->dev, "failed to retrieve <max-speed> from device tree\n");
err = -EINVAL;
goto out;
}
ndev->irq = irq;
dev_info(&pdev->dev, "IRQ is %d\n", ndev->irq);
/* Register interrupt handler for device */
err = devm_request_irq(&pdev->dev, ndev->irq, arc_emac_intr, 0,
ndev->name, ndev);
if (err) {
dev_err(&pdev->dev, "could not allocate IRQ\n");
goto out;
}
/* Get MAC address from device tree */
mac_addr = of_get_mac_address(pdev->dev.of_node);
if (mac_addr)
memcpy(ndev->dev_addr, mac_addr, ETH_ALEN);
else
eth_hw_addr_random(ndev);
dev_info(&pdev->dev, "MAC address is now %pM\n", ndev->dev_addr);
/* Do 1 allocation instead of 2 separate ones for Rx and Tx BD rings */
priv->rxbd = dmam_alloc_coherent(&pdev->dev, RX_RING_SZ + TX_RING_SZ,
&priv->rxbd_dma, GFP_KERNEL);
if (!priv->rxbd) {
dev_err(&pdev->dev, "failed to allocate data buffers\n");
err = -ENOMEM;
goto out;
}
priv->txbd = priv->rxbd + RX_BD_NUM;
priv->txbd_dma = priv->rxbd_dma + RX_RING_SZ;
dev_dbg(&pdev->dev, "EMAC Device addr: Rx Ring [0x%x], Tx Ring[%x]\n",
(unsigned int)priv->rxbd_dma, (unsigned int)priv->txbd_dma);
err = arc_mdio_probe(pdev, priv);
if (err) {
dev_err(&pdev->dev, "failed to probe MII bus\n");
goto out;
}
priv->phy_dev = of_phy_connect(ndev, phy_node, arc_emac_adjust_link, 0,
PHY_INTERFACE_MODE_MII);
if (!priv->phy_dev) {
dev_err(&pdev->dev, "of_phy_connect() failed\n");
err = -ENODEV;
goto out;
}
dev_info(&pdev->dev, "connected to %s phy with id 0x%x\n",
priv->phy_dev->drv->name, priv->phy_dev->phy_id);
netif_napi_add(ndev, &priv->napi, arc_emac_poll, ARC_EMAC_NAPI_WEIGHT);
err = register_netdev(ndev);
if (err) {
netif_napi_del(&priv->napi);
dev_err(&pdev->dev, "failed to register network device\n");
goto out;
}
return 0;
out:
free_netdev(ndev);
return err;
}
static int arc_emac_probe(struct device_d *dev)
{
struct eth_device *edev;
struct arc_emac_priv *priv;
unsigned int clock_frequency;
struct mii_bus *miibus;
u32 id;
/* Get CPU clock frequency from device tree */
if (of_property_read_u32(dev->device_node, "clock-frequency",
&clock_frequency)) {
dev_err(dev, "failed to retrieve <clock-frequency> from device tree\n");
return -EINVAL;
}
edev = xzalloc(sizeof(struct eth_device) +
sizeof(struct arc_emac_priv));
edev->priv = (struct arc_emac_priv *)(edev + 1);
miibus = xzalloc(sizeof(struct mii_bus));
priv = edev->priv;
priv->regs = dev_request_mem_region(dev, 0);
if (IS_ERR(priv->regs))
return PTR_ERR(priv->regs);
priv->bus = miibus;
id = arc_reg_get(priv, R_ID);
/* Check for EMAC revision 5 or 7, magic number */
if (!(id == 0x0005fd02 || id == 0x0007fd02)) {
dev_err(dev, "ARC EMAC not detected, id=0x%x\n", id);
free(edev);
free(miibus);
return -ENODEV;
}
dev_info(dev, "ARC EMAC detected with id: 0x%x\n", id);
edev->init = arc_emac_init;
edev->open = arc_emac_open;
edev->send = arc_emac_send;
edev->recv = arc_emac_recv;
edev->halt = arc_emac_halt;
edev->get_ethaddr = arc_emac_get_ethaddr;
edev->set_ethaddr = arc_emac_set_ethaddr;
edev->parent = dev;
miibus->read = arc_emac_mdio_read;
miibus->write = arc_emac_mdio_write;
miibus->priv = priv;
miibus->parent = dev;
/* allocate rx/tx descriptors */
priv->rxbd = dma_alloc_coherent(RX_BD_NUM * sizeof(struct arc_emac_bd));
priv->txbd = dma_alloc_coherent(TX_BD_NUM * sizeof(struct arc_emac_bd));
priv->rxbuf = dma_alloc(RX_BD_NUM * PKTSIZE);
/* Set poll rate so that it polls every 1 ms */
arc_reg_set(priv, R_POLLRATE, clock_frequency / 1000000);
/* Disable interrupts */
arc_reg_set(priv, R_ENABLE, 0);
mdiobus_register(miibus);
eth_register(edev);
return 0;
}
/**
* arc_reg_clr - Applies mask to specified EMAC register - ("reg" & ~"mask").
* @priv: Pointer to ARC EMAC private data structure.
* @reg: Register offset from base address.
* @mask: Mask to apply to specified register.
*
* This function reads initial register value, then applies provided mask
* to it and then writes register back.
*/
static inline void arc_reg_clr(struct arc_emac_priv *priv, int reg, int mask)
{
unsigned int value = arc_reg_get(priv, reg);
arc_reg_set(priv, reg, value & ~mask);
}