ir_node *be_new_Perm(arch_register_class_t const *const cls,
ir_node *const block, int const n,
ir_node *const *const in)
{
ir_graph *irg = get_irn_irg(block);
ir_node *irn = new_ir_node(NULL, irg, block, op_be_Perm, mode_T, n, in);
init_node_attr(irn, n, arch_irn_flags_none);
be_node_attr_t *attr = (be_node_attr_t*)get_irn_generic_attr(irn);
attr->exc.pin_state = op_pin_state_pinned;
for (int i = 0; i < n; ++i) {
const ir_node *input = in[i];
const arch_register_req_t *req = arch_get_irn_register_req(input);
if (req->width == 1) {
be_node_set_register_req_in(irn, i, cls->class_req);
arch_set_irn_register_req_out(irn, i, cls->class_req);
} else {
arch_register_req_t *const new_req = allocate_reg_req(irg);
new_req->cls = cls;
new_req->width = req->width;
new_req->aligned = req->aligned;
be_node_set_register_req_in(irn, i, new_req);
arch_set_irn_register_req_out(irn, i, new_req);
}
}
return irn;
}
ir_node *be_new_Start(ir_graph *const irg, be_start_out const *const outs)
{
ir_node *const block = get_irg_start_block(irg);
ir_node *const start = new_ir_node(NULL, irg, block, op_be_Start, mode_T, 0, NULL);
unsigned const n_regs = isa_if->n_registers;
/* Count the number of outsputs. */
unsigned k = 1; /* +1 for memory */
for (unsigned i = 0; i != n_regs; ++i) {
if (outs[i] != BE_START_NO)
++k;
}
be_info_init_irn(start, arch_irn_flag_schedule_first, NULL, k);
/* Set out requirements and registers. */
unsigned l = 0;
arch_set_irn_register_req_out(start, l++, arch_memory_req);
arch_register_t const *const regs = isa_if->registers;
for (unsigned i = 0; i != n_regs; ++i) {
if (outs[i] != BE_START_NO) {
arch_register_t const *const reg = ®s[i];
bool const ignore = outs[i] == BE_START_IGNORE;
arch_register_req_t const *const req = be_create_reg_req(irg, reg, ignore);
arch_set_irn_register_req_out(start, l, req);
arch_set_irn_register_out( start, l, reg);
++l;
}
}
assert(l == k);
return start;
}
ir_node *be_transform_phi(ir_node *node, const arch_register_req_t *req)
{
ir_node *block = be_transform_nodes_block(node);
ir_graph *irg = get_irn_irg(block);
dbg_info *dbgi = get_irn_dbg_info(node);
/* phi nodes allow loops, so we use the old arguments for now
* and fix this later */
ir_node **ins = get_irn_in(node)+1;
int arity = get_irn_arity(node);
ir_mode *mode = req->cls != NULL ? req->cls->mode : get_irn_mode(node);
ir_node *phi = new_ir_node(dbgi, irg, block, op_Phi, mode, arity, ins);
copy_node_attr(irg, node, phi);
backend_info_t *info = be_get_info(phi);
info->in_reqs = be_allocate_in_reqs(irg, arity);
for (int i = 0; i < arity; ++i) {
info->in_reqs[i] = req;
}
arch_set_irn_register_req_out(phi, 0, req);
be_enqueue_preds(node);
return phi;
}
void init_arm_SwitchJmp_attributes(ir_node *res, const ir_switch_table *table)
{
arm_SwitchJmp_attr_t *attr = get_arm_SwitchJmp_attr(res);
attr->table = table;
be_foreach_out(res, o) {
arch_set_irn_register_req_out(res, o, arch_exec_req);
}
static void init_sparc_switch_jmp_attributes(ir_node *node,
const ir_switch_table *table,
ir_entity *table_entity)
{
sparc_switch_jmp_attr_t *attr = get_sparc_switch_jmp_attr(node);
attr->table = table;
attr->table_entity = table_entity;
be_foreach_out(node, o) {
arch_set_irn_register_req_out(node, o, arch_no_register_req);
}
ir_node *be_new_AnyVal(ir_node *block, const arch_register_class_t *cls)
{
ir_graph *irg = get_irn_irg(block);
ir_mode *mode = cls->mode;
ir_node *res = new_ir_node(NULL, irg, block, op_be_AnyVal, mode, 0, NULL);
init_node_attr(res, 1, arch_irn_flags_none);
arch_set_irn_register_req_out(res, 0, cls->class_req);
be_node_attr_t *attr = (be_node_attr_t*)get_irn_generic_attr(res);
attr->exc.pin_state = op_pin_state_floats;
return res;
}
void be_make_start_out(be_start_info_t *const info, ir_node *const start,
unsigned const pos, arch_register_t const *const reg,
bool const ignore)
{
info->pos = pos;
info->irn = NULL;
arch_register_req_t const *const req = ignore
? be_create_reg_req(be_get_be_obst(get_irn_irg(start)), reg, true)
: reg->single_req;
arch_set_irn_register_req_out(start, pos, req);
arch_set_irn_register_out(start, pos, reg);
}
static void init_ia32_switch_attributes(ir_node *node,
const ir_switch_table *table)
{
ia32_switch_attr_t *attr = (ia32_switch_attr_t*) get_irn_generic_attr(node);
#ifndef NDEBUG
attr->attr.attr_type |= IA32_ATTR_ia32_switch_attr_t;
#endif
attr->table = table;
be_foreach_out(node, o) {
arch_set_irn_register_req_out(node, o, arch_no_register_req);
}
static void set_copy_info(ir_node *const irn, ir_graph *const irg, ir_node *const op, arch_irn_flags_t const flags)
{
init_node_attr(irn, 1, flags);
arch_register_req_t const *const op_req = arch_get_irn_register_req(op);
arch_register_class_t const *const cls = op_req->cls;
be_node_set_register_req_in(irn, 0, cls->class_req);
arch_register_req_t *const out_req = be_create_cls_req(irg, cls, op_req->width);
out_req->should_be_same = 1U << 0;
arch_set_irn_register_req_out(irn, 0, out_req);
}
ir_node *be_new_Perm(ir_node *const block, int const n, ir_node *const *const in)
{
ir_graph *const irg = get_irn_irg(block);
ir_node *const irn = new_ir_node(NULL, irg, block, op_be_Perm, mode_T, n, in);
init_node_attr(irn, n, arch_irn_flags_none);
for (int i = 0; i < n; ++i) {
arch_register_req_t const *const in_req = arch_get_irn_register_req(in[i]);
arch_register_req_t const *const slot_req =
in_req->width == 1 ? in_req->cls->class_req :
be_create_cls_req(irg, in_req->cls, in_req->width);
be_node_set_register_req_in( irn, i, slot_req);
arch_set_irn_register_req_out(irn, i, slot_req);
}
return irn;
}
ir_node *be_new_MemPerm(ir_node *const block, int n, ir_node *const *const in)
{
ir_graph *const irg = get_irn_irg(block);
ir_node *const irn = new_ir_node(NULL, irg, block, op_be_MemPerm, mode_T, n, in);
init_node_attr(irn, n, arch_irn_flags_none);
for (int i = 0; i < n; ++i) {
be_node_set_register_req_in( irn, i, arch_memory_req);
arch_set_irn_register_req_out(irn, i, arch_memory_req);
}
be_memperm_attr_t *attr = (be_memperm_attr_t*)get_irn_generic_attr(irn);
attr->in_entities = OALLOCNZ(get_irg_obstack(irg), ir_entity*, n);
attr->out_entities = OALLOCNZ(get_irg_obstack(irg), ir_entity*, n);
attr->offset = 0;
return irn;
}
static void set_copy_info(ir_node *const irn, ir_graph *const irg, ir_node *const op, arch_irn_flags_t const flags)
{
init_node_attr(irn, 1, flags);
be_node_attr_t *const attr = (be_node_attr_t*)get_irn_generic_attr(irn);
attr->exc.pin_state = op_pin_state_floats;
arch_register_req_t const *const op_req = arch_get_irn_register_req(op);
arch_register_class_t const *const cls = op_req->cls;
be_node_set_register_req_in(irn, 0, cls->class_req);
arch_register_req_t *const out_req = allocate_reg_req(irg);
out_req->cls = cls;
out_req->should_be_same = 1U << 0;
out_req->aligned = op_req->aligned;
out_req->width = op_req->width;
arch_set_irn_register_req_out(irn, 0, out_req);
}
void be_make_start_mem(be_start_info_t *const info, ir_node *const start, unsigned const pos)
{
info->pos = pos;
info->irn = NULL;
arch_set_irn_register_req_out(start, pos, arch_no_register_req);
}
