/* * Perform the very early platform specific architectural setup here. At the * moment this is only intializes the MMU in a quick and dirty way. */ void bl31_plat_arch_setup(void) { plat_arm_interconnect_init(); plat_arm_interconnect_enter_coherency(); arm_configure_mmu_el3(BL31_RO_BASE, BL31_COHERENT_RAM_LIMIT - BL31_RO_BASE, BL31_RO_BASE, BL31_RO_LIMIT, BL31_COHERENT_RAM_BASE, BL31_COHERENT_RAM_LIMIT); }
/******************************************************************************* * Perform the very early platform specific architectural setup here. At the * moment this is only intializes the mmu in a quick and dirty way. ******************************************************************************/ void arm_bl31_plat_arch_setup(void) { arm_configure_mmu_el3(BL31_RO_BASE, (BL31_END - BL31_RO_BASE), BL31_RO_BASE, BL31_RO_LIMIT #if USE_COHERENT_MEM , BL31_COHERENT_RAM_BASE, BL31_COHERENT_RAM_LIMIT #endif ); }
/******************************************************************************* * Perform the very early platform specific architectural setup here. At the * moment this is only intializes the mmu in a quick and dirty way. ******************************************************************************/ void bl31_plat_arch_setup(void) { zynqmp_cci_init(); zynqmp_cci_enable(); arm_configure_mmu_el3(BL31_RO_BASE, BL31_COHERENT_RAM_LIMIT - BL31_RO_BASE, BL31_RO_BASE, BL31_RO_LIMIT, BL31_COHERENT_RAM_BASE, BL31_COHERENT_RAM_LIMIT); }