Example #1
0
File: mmu.c Project: machinaut/lk
void arm_mmu_unmap_section(addr_t vaddr)
{
	uint index = vaddr / MB;
	tt[index] = 0;

	arm_invalidate_tlb();
}
Example #2
0
void arm_mmu_map_section(addr_t paddr, addr_t vaddr, uint flags)
{
	int index;
	uint AP;
	uint CB;
	uint TEX = 0;

	// XXX: move platform dependent codes
#if defined(PLATFORM_MSM7K)
	if ((paddr >= 0x88000000) && (paddr < 0xD0000000)) {
            /* peripherals in the 0x88000000 - 0xD0000000 range must
             * be mapped as DEVICE NON-SHARED: TEX=2, C=0, B=0
             */
		TEX = 2;
		flags &= (~(MMU_FLAG_CACHED | MMU_FLAG_BUFFERED));
	}
#endif
#if defined(PLATFORM_TCC88XX) || defined(PLATFORM_TCC92XX)
	if ((paddr >= 0xF0000000) && (paddr <= 0xFFFFFFFF)) {
		TEX = 2;
		flags &= (~(MMU_FLAG_CACHED | MMU_FLAG_BUFFERED));
	}
#endif
#if defined(PLATFORM_TCC892X)
	if ((paddr >= 0x00000000) && (paddr < 0x20000000)) {
		flags &= (~(MMU_FLAG_CACHED | MMU_FLAG_BUFFERED));
	}
	if ((paddr >= 0x60000000) && (paddr < 0x80000000)) {
		TEX = 2;
		flags &= (~(MMU_FLAG_CACHED | MMU_FLAG_BUFFERED));
	}
#endif
#if defined(PLATFORM_TCC93XX)
	if ((paddr >= 0xB0000000) && (paddr <= 0xBFFFFFFF)) {
		TEX = 2;
		flags &= (~(MMU_FLAG_CACHED | MMU_FLAG_BUFFERED));
	}
#endif

#ifdef WITH_DMA_ZONE
	if ((paddr >= dma_base()) && (paddr < (dma_base() + dma_size()))) {
		flags &= (~(MMU_FLAG_CACHED | MMU_FLAG_BUFFERED));
	}
#endif

	AP = (flags & MMU_FLAG_READWRITE) ? 0x3 : 0x2;
	CB = ((flags & MMU_FLAG_CACHED) ? 0x2 : 0) | ((flags & MMU_FLAG_BUFFERED) ? 0x1 : 0);

	index = vaddr / MB;
	// section mapping
	tt[index] = (paddr & ~(MB-1)) | (TEX << 12) | (AP << 10) | (0<<5) | (CB << 2) | (2<<0);

	arm_invalidate_tlb();
}
Example #3
0
File: mmu.c Project: machinaut/lk
void arm_mmu_map_section(addr_t paddr, addr_t vaddr, uint flags)
{
	int index;
	uint AP;
	uint CB = 0;
	uint TEX = 0;

#if defined(PLATFORM_MSM7K)
	if ((paddr >= 0x88000000) && (paddr < 0xD0000000)) {
		/* peripherals in the 0x88000000 - 0xD0000000 range must
		 * be mapped as DEVICE NON-SHARED: TEX=2, C=0, B=0
		 */
		TEX = 2;
		flags &= (~(MMU_FLAG_CACHED | MMU_FLAG_BUFFERED));
	}
#endif

	AP = (flags & MMU_FLAG_READWRITE) ? 0x3 : 0x2;
#if 1
	CB = ((flags & MMU_FLAG_CACHED) ? 0x2 : 0) | ((flags & MMU_FLAG_BUFFERED) ? 0x1 : 0);
#elif 0
	CB = ((flags & MMU_FLAG_CACHED) ? 0x2 : 0) | ((flags & MMU_FLAG_BUFFERED) ? 0x1 : 0);
	if (CB) {
		TEX = 1; // full write allocate on all levels
	}
#elif 0
	// try out some of the extended TEX options
	if (flags & MMU_FLAG_CACHED) {
		TEX = 6;
		CB = 3;
	}
#endif

	index = vaddr / MB;

	// section mapping
	tt[index] = (paddr & ~(MB-1)) | (TEX << 12) | (AP << 10) | (0<<5) | (CB << 2) | (2<<0);

	arm_invalidate_tlb();
}