void at86rf2xx_reset(at86rf2xx_t *dev)
{
eui64_t addr_long;
at86rf2xx_hardware_reset(dev);
/* Reset state machine to ensure a known state */
at86rf2xx_reset_state_machine(dev);
/* reset options and sequence number */
dev->netdev.seq = 0;
dev->netdev.flags = 0;
/* get an 8-byte unique ID to use as hardware address */
luid_get(addr_long.uint8, IEEE802154_LONG_ADDRESS_LEN);
/* make sure we mark the address as non-multicast and not globally unique */
addr_long.uint8[0] &= ~(0x01);
addr_long.uint8[0] |= (0x02);
/* set short and long address */
at86rf2xx_set_addr_long(dev, NTOHLL(addr_long.uint64.u64));
at86rf2xx_set_addr_short(dev, NTOHS(addr_long.uint16[0].u16));
/* set default PAN id */
at86rf2xx_set_pan(dev, AT86RF2XX_DEFAULT_PANID);
/* set default channel */
at86rf2xx_set_chan(dev, AT86RF2XX_DEFAULT_CHANNEL);
/* set default TX power */
at86rf2xx_set_txpower(dev, AT86RF2XX_DEFAULT_TXPOWER);
/* set default options */
at86rf2xx_set_option(dev, AT86RF2XX_OPT_AUTOACK, true);
at86rf2xx_set_option(dev, AT86RF2XX_OPT_CSMA, true);
at86rf2xx_set_option(dev, AT86RF2XX_OPT_TELL_RX_START, false);
at86rf2xx_set_option(dev, AT86RF2XX_OPT_TELL_RX_END, true);
#ifdef MODULE_NETSTATS_L2
at86rf2xx_set_option(dev, AT86RF2XX_OPT_TELL_TX_END, true);
#endif
/* set default protocol */
#ifdef MODULE_GNRC_SIXLOWPAN
dev->netdev.proto = GNRC_NETTYPE_SIXLOWPAN;
#elif MODULE_GNRC
dev->netdev.proto = GNRC_NETTYPE_UNDEF;
#endif
/* enable safe mode (protect RX FIFO until reading data starts) */
at86rf2xx_reg_write(dev, AT86RF2XX_REG__TRX_CTRL_2,
AT86RF2XX_TRX_CTRL_2_MASK__RX_SAFE_MODE);
#ifdef MODULE_AT86RF212B
at86rf2xx_set_page(dev, 0);
#endif
/* don't populate masked interrupt flags to IRQ_STATUS register */
uint8_t tmp = at86rf2xx_reg_read(dev, AT86RF2XX_REG__TRX_CTRL_1);
tmp &= ~(AT86RF2XX_TRX_CTRL_1_MASK__IRQ_MASK_MODE);
at86rf2xx_reg_write(dev, AT86RF2XX_REG__TRX_CTRL_1, tmp);
/* disable clock output to save power */
tmp = at86rf2xx_reg_read(dev, AT86RF2XX_REG__TRX_CTRL_0);
tmp &= ~(AT86RF2XX_TRX_CTRL_0_MASK__CLKM_CTRL);
tmp &= ~(AT86RF2XX_TRX_CTRL_0_MASK__CLKM_SHA_SEL);
tmp |= (AT86RF2XX_TRX_CTRL_0_CLKM_CTRL__OFF);
at86rf2xx_reg_write(dev, AT86RF2XX_REG__TRX_CTRL_0, tmp);
/* enable interrupts */
at86rf2xx_reg_write(dev, AT86RF2XX_REG__IRQ_MASK,
AT86RF2XX_IRQ_STATUS_MASK__TRX_END);
/* clear interrupt flags */
at86rf2xx_reg_read(dev, AT86RF2XX_REG__IRQ_STATUS);
/* go into RX state */
at86rf2xx_set_state(dev, AT86RF2XX_STATE_RX_AACK_ON);
DEBUG("at86rf2xx_reset(): reset complete.\n");
}
void at86rf2xx_reset(at86rf2xx_t *dev)
{
#if CPUID_LEN
uint8_t cpuid[CPUID_LEN];
eui64_t addr_long;
#endif
at86rf2xx_hardware_reset(dev);
/* Reset state machine to ensure a known state */
at86rf2xx_reset_state_machine(dev);
/* reset options and sequence number */
dev->seq_nr = 0;
dev->options = 0;
/* set short and long address */
#if CPUID_LEN
cpuid_get(cpuid);
#if CPUID_LEN < 8
/* in case CPUID_LEN < 8, fill missing bytes with zeros */
for (int i = CPUID_LEN; i < 8; i++) {
cpuid[i] = 0;
}
#else
for (int i = 8; i < CPUID_LEN; i++) {
cpuid[i & 0x07] ^= cpuid[i];
}
#endif
/* make sure we mark the address as non-multicast and not globally unique */
cpuid[0] &= ~(0x01);
cpuid[0] |= 0x02;
/* copy and set long address */
memcpy(&addr_long, cpuid, 8);
at86rf2xx_set_addr_long(dev, NTOHLL(addr_long.uint64.u64));
at86rf2xx_set_addr_short(dev, NTOHS(addr_long.uint16[0].u16));
#else
at86rf2xx_set_addr_long(dev, AT86RF2XX_DEFAULT_ADDR_LONG);
at86rf2xx_set_addr_short(dev, AT86RF2XX_DEFAULT_ADDR_SHORT);
#endif
/* set default PAN id */
at86rf2xx_set_pan(dev, AT86RF2XX_DEFAULT_PANID);
/* set default channel */
at86rf2xx_set_chan(dev, AT86RF2XX_DEFAULT_CHANNEL);
/* set default TX power */
at86rf2xx_set_txpower(dev, AT86RF2XX_DEFAULT_TXPOWER);
/* set default options */
at86rf2xx_set_option(dev, AT86RF2XX_OPT_AUTOACK, true);
at86rf2xx_set_option(dev, AT86RF2XX_OPT_CSMA, true);
at86rf2xx_set_option(dev, AT86RF2XX_OPT_TELL_RX_START, false);
at86rf2xx_set_option(dev, AT86RF2XX_OPT_TELL_RX_END, true);
/* set default protocol */
#ifdef MODULE_GNRC_SIXLOWPAN
dev->proto = GNRC_NETTYPE_SIXLOWPAN;
#else
dev->proto = GNRC_NETTYPE_UNDEF;
#endif
/* enable safe mode (protect RX FIFO until reading data starts) */
at86rf2xx_reg_write(dev, AT86RF2XX_REG__TRX_CTRL_2,
AT86RF2XX_TRX_CTRL_2_MASK__RX_SAFE_MODE);
#ifdef MODULE_AT86RF212B
at86rf2xx_set_page(dev, 0);
#endif
/* don't populate masked interrupt flags to IRQ_STATUS register */
uint8_t tmp = at86rf2xx_reg_read(dev, AT86RF2XX_REG__TRX_CTRL_1);
tmp &= ~(AT86RF2XX_TRX_CTRL_1_MASK__IRQ_MASK_MODE);
at86rf2xx_reg_write(dev, AT86RF2XX_REG__TRX_CTRL_1, tmp);
/* disable clock output to save power */
tmp = at86rf2xx_reg_read(dev, AT86RF2XX_REG__TRX_CTRL_0);
tmp &= ~(AT86RF2XX_TRX_CTRL_0_MASK__CLKM_CTRL);
tmp &= ~(AT86RF2XX_TRX_CTRL_0_MASK__CLKM_SHA_SEL);
tmp |= (AT86RF2XX_TRX_CTRL_0_CLKM_CTRL__OFF);
at86rf2xx_reg_write(dev, AT86RF2XX_REG__TRX_CTRL_0, tmp);
/* enable interrupts */
at86rf2xx_reg_write(dev, AT86RF2XX_REG__IRQ_MASK,
AT86RF2XX_IRQ_STATUS_MASK__TRX_END);
/* clear interrupt flags */
at86rf2xx_reg_read(dev, AT86RF2XX_REG__IRQ_STATUS);
/* go into RX state */
at86rf2xx_set_state(dev, AT86RF2XX_STATE_RX_AACK_ON);
DEBUG("at86rf2xx_reset(): reset complete.\n");
}
