static void at91sam9260ek_phy_reset(void)
{
unsigned long rstc;
at91_pmc_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_EMAC);
at91_set_gpio_input(AT91_PIN_PA14, 0);
at91_set_gpio_input(AT91_PIN_PA15, 0);
at91_set_gpio_input(AT91_PIN_PA17, 0);
at91_set_gpio_input(AT91_PIN_PA25, 0);
at91_set_gpio_input(AT91_PIN_PA26, 0);
at91_set_gpio_input(AT91_PIN_PA28, 0);
rstc = at91_sys_read(AT91_RSTC_MR) & AT91_RSTC_ERSTL;
/* Need to reset PHY -> 500ms reset */
at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
(AT91_RSTC_ERSTL & (0x0d << 8)) |
AT91_RSTC_URSTEN);
at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST);
/* Wait for end hardware reset */
while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL));
/* Restore NRST value */
at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
(rstc) |
AT91_RSTC_URSTEN);
}
static void at91rm9200_idle(void)
{
/*
* Disable the processor clock. The processor will be automatically
* re-enabled by an interrupt or by a reset.
*/
at91_pmc_write(AT91_PMC_SCDR, AT91_PMC_PCK);
}
void at91sam9_idle(void)
{
at91_pmc_write(AT91_PMC_SCDR, AT91_PMC_PCK);
cpu_do_idle();
}
static void at91rm9200_idle(void)
{
at91_pmc_write(AT91_PMC_SCDR, AT91_PMC_PCK);
}
void __bare_init at91sam926x_lowlevel_init(struct at91sam926x_lowlevel_cfg *cfg)
{
u32 r;
int in_sram = running_in_sram();
at91sam926x_lowlevel_board_config(cfg);
__raw_writel(cfg->wdt_mr, AT91_BASE_WDT + AT91_WDT_MR);
/* configure PIOx as EBI0 D[16-31] */
at91_mux_gpio_disable(cfg->pio, cfg->ebi_pio_pdr);
at91_mux_set_pullup(cfg->pio, cfg->ebi_pio_ppudr, true);
if (cfg->ebi_pio_is_peripha)
at91_mux_set_A_periph(cfg->pio, cfg->ebi_pio_ppudr);
at91_sys_write(cfg->matrix_csa, cfg->ebi_csa);
/* flash */
at91_smc_write(cfg->smc_cs, AT91_SAM9_SMC_MODE, cfg->smc_mode);
at91_smc_write(cfg->smc_cs, AT91_SMC_CYCLE, cfg->smc_cycle);
at91_smc_write(cfg->smc_cs, AT91_SMC_PULSE, cfg->smc_pulse);
at91_smc_write(cfg->smc_cs, AT91_SMC_SETUP, cfg->smc_setup);
/*
* PMC Check if the PLL is already initialized
*/
r = at91_pmc_read(AT91_PMC_MCKR);
if (r & AT91_PMC_CSS && !in_sram)
return;
/*
* Enable the Main Oscillator
*/
at91_pmc_write(AT91_CKGR_MOR, cfg->pmc_mor);
do {
r = at91_pmc_read(AT91_PMC_SR);
} while (!(r & AT91_PMC_MOSCS));
/*
* PLLAR: x MHz for PCK
*/
at91_pmc_write(AT91_CKGR_PLLAR, cfg->pmc_pllar);
do {
r = at91_pmc_read(AT91_PMC_SR);
} while (!(r & AT91_PMC_LOCKA));
/*
* PCK/x = MCK Master Clock from SLOW
*/
at91_pmc_write(AT91_PMC_MCKR, cfg->pmc_mckr1);
pmc_check_mckrdy();
/*
* PCK/x = MCK Master Clock from PLLA
*/
at91_pmc_write(AT91_PMC_MCKR, cfg->pmc_mckr2);
pmc_check_mckrdy();
/*
* Init SDRAM
*/
at91sam926x_sdramc_init(cfg);
/* User reset enable*/
at91_sys_write(AT91_RSTC_MR, cfg->rstc_rmr);
#ifdef CONFIG_SYS_MATRIX_MCFG_REMAP
/* MATRIX_MCFG - REMAP all masters */
at91_sys_write(AT91_MATRIX_MCFG0, 0x1FF);
#endif
/*
* When boot from external boot
* we need to enable mck and ohter clock
* so enable all of them
* We will shutdown what we don't need later
*/
at91_pmc_write(AT91_PMC_PCER, 0xffffffff);
}
