/* Force a reset of the playback amplifier */
static void ipspeaker_tas5709_reset(void)
{
at91_set_gpio_value(AT91_PIN_PB2, 0);
udelay(200);
at91_set_gpio_value(AT91_PIN_PB2, 1);
mdelay(20); /* something > 13.5 msec */
}
void gurnard_usb_init(void)
{
at91_set_gpio_output(USB0_ENABLE_PIN, 1);
at91_set_gpio_value(USB0_ENABLE_PIN, 0);
at91_set_gpio_output(USB1_ENABLE_PIN, 1);
at91_set_gpio_value(USB1_ENABLE_PIN, 0);
}
static void at91_lcdc_tft_power_control(int on)
{
if (on)
at91_set_gpio_value(AT91_PIN_PA12, 0); /* power up */
else
at91_set_gpio_value(AT91_PIN_PA12, 1); /* power down */
}
void gprs_powerdown(int which)
{
if (POWEROFF == gprs_powermon(which)) /*Alread power off */
return;
dbg_print("Power down %s module.\n", support_gprs[which].name);
// Currently it is power on
/*step1: turn off vbus*/
if (GSM_UC864E == which || GSM_SIM521X == which)
{
at91_set_gpio_output (GPRS_VBUS_CTRL_PIN, LOWLEVEL);
SLEEP (100);
}
/*step 2: turn off gprs module*/
#ifdef PLAT_L2
at91_set_gpio_value (GPRS_ON_PIN, HIGHLEVEL);
#else
at91_set_gpio_value (GPRS_ON_PIN, LOWLEVEL);
#endif
SLEEP(support_gprs[which].poweroff_period_time);
#ifdef PLAT_L2
at91_set_gpio_value (GPRS_ON_PIN, LOWLEVEL);
at91_set_gpio_output (GPRS_38V_ON_PIN, LOWLEVEL); //gprs module power on init
#else
at91_set_gpio_value (GPRS_ON_PIN, HIGHLEVEL);
#endif
dbg_print("Delay for %ld ms wait for AT command shutdown\n", support_gprs[which].atcmd_inactive_time);
SLEEP(support_gprs[which].atcmd_inactive_time);
}
void spi_cs_deactivate(struct spi_slave *slave)
{
if(slave->cs == 0)
at91_set_gpio_value(SBC_A9260_CS0_PIN, 1);
else if(slave->cs == 1)
at91_set_gpio_value(SBC_A9260_CS1_PIN, 1);
}
static void at91_lcdc_power_control(int on)
{
if (on)
at91_set_gpio_value(AT91_PIN_PC1, 0);
else
at91_set_gpio_value(AT91_PIN_PC1, 1);
}
static int
at91_cf_set_socket(struct pcmcia_socket *sock, struct socket_state_t *s)
{
struct at91_cf_socket *cf;
cf = container_of(sock, struct at91_cf_socket, socket);
/* switch Vcc if needed and possible */
if (cf->board->vcc_pin) {
switch (s->Vcc) {
case 0:
at91_set_gpio_value(cf->board->vcc_pin, 0);
break;
case 33:
at91_set_gpio_value(cf->board->vcc_pin, 1);
break;
default:
return -EINVAL;
}
}
/* toggle reset if needed */
at91_set_gpio_value(cf->board->rst_pin, s->flags & SS_RESET);
pr_debug("%s: Vcc %d, io_irq %d, flags %04x csc %04x\n",
driver_name, s->Vcc, s->io_irq, s->flags, s->csc_mask);
return 0;
}
void gprs_powerup(int which)
{
dbg_print("Power up %s module.\n", support_gprs[which].name);
/*USB 3G GPRS module power up procedure will goes here, till now, only UC864E support it*/
if (POWERON == gprs_powermon(which))
{
gprs_reset(which); /*If GPRS module already power up, then we reset it */
return;
}
//Currently it is power off
#ifdef PLAT_L2
dbg_print("Enable GPRS_38V_ON_PIN.\n");
if (GSM_SIM900X == which)
{
at91_set_gpio_output (GPRS_RESET_PIN, LOWLEVEL); //gprs module power on init
}
at91_set_gpio_output (GPRS_38V_ON_PIN, HIGHLEVEL); //gprs module power on init
#endif
/*step1: turn off vbus for 3G module*/
if (GSM_UC864E == which || GSM_SIM521X == which)
{
at91_set_gpio_output (GPRS_VBUS_CTRL_PIN, LOWLEVEL);
SLEEP (100);
}
/*step2: power on gprs module*/
#ifdef PLAT_L2
at91_set_gpio_value (GPRS_ON_PIN, HIGHLEVEL);
#else
at91_set_gpio_value (GPRS_ON_PIN, LOWLEVEL);
#endif
SLEEP(support_gprs[which].poweron_period_time);
#ifdef PLAT_L2
at91_set_gpio_value (GPRS_ON_PIN, LOWLEVEL);
#else
at91_set_gpio_value (GPRS_ON_PIN, HIGHLEVEL);
#endif
#ifdef PLAT_L2
if (GSM_SIM900X == which)
{
at91_set_gpio_output (GPRS_DTR_PIN, LOWLEVEL); //gprs module power on init
msleep(50);
}
#endif
/*step3: Turn on vbus for 3G module*/
if (GSM_UC864E == which || GSM_SIM521X == which)
{
at91_set_gpio_output (GPRS_VBUS_CTRL_PIN, HIGHLEVEL);
}
dbg_print("Delay for %ld ms wait for AT command ready\n", support_gprs[which].atcmd_active_time);
SLEEP(support_gprs[which].atcmd_active_time);
}
static int at91mc323_reset(void)
{
at91_set_gpio_value(MC323_RST, HIGH);
at91_set_gpio_value(MC323_RST, LOW);
mdelay(20);
at91_set_gpio_value(MC323_RST, HIGH);
return 0;
}
static int at91mc323_poweron(void)
{
at91_set_gpio_value(MC323_POWERON, HIGH);
at91_set_gpio_value(MC323_POWERON, LOW);
mdelay(200);
at91_set_gpio_value(MC323_POWERON, HIGH);
return 0;
}
void coloured_LED_init(void)
{
/* Clock is enabled in board_early_init_f() */
at91_set_gpio_output(CONFIG_RED_LED, 1);
at91_set_gpio_output(CONFIG_GREEN_LED, 1);
at91_set_gpio_value(CONFIG_RED_LED, 0);
at91_set_gpio_value(CONFIG_GREEN_LED, 1);
}
void coloured_LED_init(void)
{
/* Enable clock */
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOA);
at91_set_gpio_output(RED_LED, 1);
at91_set_gpio_output(GREEN_LED, 1);
at91_set_gpio_value(RED_LED, 0);
at91_set_gpio_value(GREEN_LED, 1);
}
void gprs_set_rts(int which, int level)
{
/*SIM521X doesn't support it */
if (GSM_SIM521X == which)
return;
if (LOWLEVEL == level)
at91_set_gpio_value (GPRS_RTS_PIN, LOWLEVEL);
else
at91_set_gpio_value (GPRS_RTS_PIN, HIGHLEVEL);
}
static void at91_lcdc_stn_power_control(int on)
{
if (on) {
at91_set_gpio_value(AT91_PIN_PC14, 0);
at91_set_gpio_value(AT91_PIN_PC15, 0);
} else {
at91_set_gpio_value(AT91_PIN_PC14, 1);
at91_set_gpio_value(AT91_PIN_PC15, 1);
}
}
static void at91_lcdc_stn_power_control(int on)
{
/* backlight */
if (on) { /* power up */
at91_set_gpio_value(AT91_PIN_PC14, 0);
at91_set_gpio_value(AT91_PIN_PC15, 0);
} else { /* power down */
at91_set_gpio_value(AT91_PIN_PC14, 1);
at91_set_gpio_value(AT91_PIN_PC15, 1);
}
}
void coloured_LED_init(void)
{
/* Enable clock */
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_PIOD);
at91_set_gpio_output(CONFIG_RED_LED, 1);
at91_set_gpio_output(CONFIG_GREEN_LED, 1);
at91_set_gpio_output(CONFIG_YELLOW_LED, 1);
at91_set_gpio_value(CONFIG_RED_LED, 0);
at91_set_gpio_value(CONFIG_GREEN_LED, 1);
at91_set_gpio_value(CONFIG_YELLOW_LED, 1);
}
void init_smc_ddr()
{
#if 0
printf("leds should change now!\n");
at91_set_gpio_output(AT91_PIN_PA0, 1);
at91_set_gpio_output(AT91_PIN_PA1, 0);
vTaskDelay(2000);
printf("leds should change now!\n");
at91_set_gpio_value(AT91_PIN_PA0, 0);
at91_set_gpio_value(AT91_PIN_PA1, 1);
#endif
/* Configure the EBI1 pins for the wr switch */
int i;
/* PC16..31: periphA as EBI1_D16..31 */
for (i = AT91_PIN_PC16; i <= AT91_PIN_PC31; i++){
at91_set_A_periph(i, 0);
}
/* PC2 and PC3 too: EBI1_A19 EBI1_A20 */
at91_set_A_periph(AT91_PIN_PC2, 0);
at91_set_A_periph(AT91_PIN_PC3, 0);
/* FIXME: We should pull rst high for when it is programmed */
/* Then, write the EBI1 configuration (NCS0 == 0x1000.0000) */
at91_sys_write(AT91_SMC_SETUP(0),
AT91_SMC_NWESETUP_(4) |
AT91_SMC_NCS_WRSETUP_(2) |
AT91_SMC_NRDSETUP_(4) |
AT91_SMC_NCS_RDSETUP_(2));
at91_sys_write(AT91_SMC_PULSE(0),
AT91_SMC_NWEPULSE_(30) |
AT91_SMC_NCS_WRPULSE_(34) |
AT91_SMC_NRDPULSE_(30) |
AT91_SMC_NCS_RDPULSE_(34));
at91_sys_write(AT91_SMC_CYCLE(0),
AT91_SMC_NWECYCLE_(40) |
AT91_SMC_NRDCYCLE_(40));
at91_sys_write(AT91_SMC_MODE(0),
AT91_SMC_DBW_32 |
AT91_SMC_TDF_(0) |
AT91_SMC_READMODE |
AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_FROZEN);
}
/*
* Set the IOS
*/
static void at91_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
{
int clkdiv;
struct at91mci_host *host = mmc_priv(mmc);
unsigned long at91_master_clock = clk_get_rate(host->mci_clk);
host->bus_mode = ios->bus_mode;
if (ios->clock == 0) {
/* Disable the MCI controller */
at91_mci_write(host, AT91_MCI_CR, AT91_MCI_MCIDIS);
clkdiv = 0;
}
else {
/* Enable the MCI controller */
at91_mci_write(host, AT91_MCI_CR, AT91_MCI_MCIEN);
if ((at91_master_clock % (ios->clock * 2)) == 0)
clkdiv = ((at91_master_clock / ios->clock) / 2) - 1;
else
clkdiv = (at91_master_clock / ios->clock) / 2;
pr_debug("clkdiv = %d. mcck = %ld\n", clkdiv,
at91_master_clock / (2 * (clkdiv + 1)));
}
if (ios->bus_width == MMC_BUS_WIDTH_4 && host->board->wire4) {
pr_debug("MMC: Setting controller bus width to 4\n");
at91_mci_write(host, AT91_MCI_SDCR, at91_mci_read(host, AT91_MCI_SDCR) | AT91_MCI_SDCBUS);
}
else {
pr_debug("MMC: Setting controller bus width to 1\n");
at91_mci_write(host, AT91_MCI_SDCR, at91_mci_read(host, AT91_MCI_SDCR) & ~AT91_MCI_SDCBUS);
}
/* Set the clock divider */
at91_mci_write(host, AT91_MCI_MR, (at91_mci_read(host, AT91_MCI_MR) & ~AT91_MCI_CLKDIV) | clkdiv);
/* maybe switch power to the card */
if (host->board->vcc_pin) {
switch (ios->power_mode) {
case MMC_POWER_OFF:
at91_set_gpio_value(host->board->vcc_pin, 0);
break;
case MMC_POWER_UP:
case MMC_POWER_ON:
at91_set_gpio_value(host->board->vcc_pin, 1);
break;
}
}
}
void coloured_LED_init(void)
{
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
/* Enable the clock */
writel(ATMEL_ID_PIOC, &pmc->pcer);
at91_set_gpio_output(CONFIG_RED_LED, 1);
at91_set_gpio_output(CONFIG_GREEN_LED, 1);
at91_set_gpio_output(CONFIG_YELLOW_LED, 1);
at91_set_gpio_value(CONFIG_RED_LED, 0);
at91_set_gpio_value(CONFIG_GREEN_LED, 1);
at91_set_gpio_value(CONFIG_YELLOW_LED, 0);
}
void coloured_LED_init(void)
{
/* Enable clock */
at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
writel(1 << ATMEL_ID_PIOB | 1 << ATMEL_ID_PIOCDE,
&pmc->pcer);
at91_set_gpio_output(CONFIG_RED_LED, 1);
at91_set_gpio_output(CONFIG_GREEN_LED, 1);
at91_set_gpio_output(CONFIG_YELLOW_LED, 1);
at91_set_gpio_value(CONFIG_RED_LED, 0);
at91_set_gpio_value(CONFIG_GREEN_LED, 1);
at91_set_gpio_value(CONFIG_YELLOW_LED, 1);
}
int gprs_set_worksim(int sim)
{
if (SIM1 != sim && SIM2 != sim)
{
printk("ERROR: Set unknow SIM%d to work.\n", sim);
return -1;
}
dbg_print("Set SIM%d work\n", sim);
if (SIM2 == sim)
at91_set_gpio_value (GPRS_SELECT_SIM_PIN, LOWLEVEL);
else
at91_set_gpio_value (GPRS_SELECT_SIM_PIN, HIGHLEVEL);
return 0;
}
void coloured_LED_init(void)
{
at91_periph_clk_enable(ATMEL_ID_PIODE);
at91_set_gpio_output(CONFIG_GREEN_LED, 1);
at91_set_gpio_value(CONFIG_GREEN_LED, 1);
}
static inline void cs_deactivate(struct spi_device *spi)
{
unsigned gpio = (unsigned) spi->controller_data;
unsigned active = spi->mode & SPI_CS_HIGH;
dev_dbg(&spi->dev, "DEactivate %u%s\n", gpio, active ? " (low)" : "");
at91_set_gpio_value(gpio, !active);
}
static void pm9g45_phy_init(void)
{
/*
* PD2 enables the 50MHz oscillator for Ethernet PHY
* 1 - enable
* 0 - disable
*/
at91_set_gpio_output(AT91_PIN_PD2, 1);
at91_set_gpio_value(AT91_PIN_PD2, 1);
}
u16 get_key_val_no_irq (void)
{
char datac,tstint;
int num;
U16 keysca;
do
{
do
{
/* ´Ó¼üÅ̽ÚƬ¶ÁÈ¡¼üÖµ */
if (Key_Read(&datac, 0x0))
printk (KERN_ALERT "Keyb chip read failed.\n");
#ifdef KEYB_DEBUG
printk (KERN_ALERT "keyirq: the key is %x\n", keysca);
#endif
if (datac == 0x0)
return 0;
num = (int) (datac & 0x3f);
keysca = raw2scancode(num);
#ifdef __NEW_KB
if (keysca == 0x0f)
{
//mdelay (15000);
pkeyb_dev->is_backlight = !at91_get_gpio_value(KEY_BL);
at91_set_gpio_value (KEY_BL, pkeyb_dev->is_backlight);
//at91_set_gpio_value (KEY_BL, !at91_get_gpio_value (KEY_BL));
}
else
{
if (!at91_get_gpio_value (KEY_SHT))
keysca |= (0x0f << 8);
//if (kbufin (keysca))
// printk (KERN_ALERT "petworm: kbufin full.\n");
}
#else
/* ½«¶ÁÈ¡µÄ¼üÖµ·ÅÈ뻺³åÇø */
if (kbufin (keysca))
printk (KERN_ALERT "petworm: kbufin full.\n");
#endif
#ifdef __NET_KB
}while (((datac & 0x40) != 0x0) || (datac != 0x0));
#else
}while (((datac & 0x40) != 0x0));
#endif
Key_Read(&tstint, 0x3);
}while ((tstint & 0x80) != 0);
/*
* Set state of the modem control output lines
*/
static void atmel_set_mctrl(struct uart_port *port, u_int mctrl)
{
unsigned int control = 0;
unsigned int mode;
#ifdef CONFIG_ARCH_AT91RM9200
if (cpu_is_at91rm9200()) {
/*
* AT91RM9200 Errata #39: RTS0 is not internally connected to PA21.
* We need to drive the pin manually.
*/
if (port->mapbase == AT91RM9200_BASE_US0) {
if (mctrl & TIOCM_RTS)
at91_set_gpio_value(AT91_PIN_PA21, 0);
else
at91_set_gpio_value(AT91_PIN_PA21, 1);
}
}
#endif
if (mctrl & TIOCM_RTS)
control |= ATMEL_US_RTSEN;
else
control |= ATMEL_US_RTSDIS;
if (mctrl & TIOCM_DTR)
control |= ATMEL_US_DTREN;
else
control |= ATMEL_US_DTRDIS;
UART_PUT_CR(port, control);
/* Local loopback mode? */
mode = UART_GET_MR(port) & ~ATMEL_US_CHMODE;
if (mctrl & TIOCM_LOOP)
mode |= ATMEL_US_CHMODE_LOC_LOOP;
else
mode |= ATMEL_US_CHMODE_NORMAL;
UART_PUT_MR(port, mode);
}
static void at91sam9260ek_nand_hwcontrol(struct mtd_info *mtd, int cmd)
{
struct nand_chip *this = mtd->priv;
ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
IO_ADDR_W &= ~(MASK_ALE|MASK_CLE);
switch (cmd) {
case NAND_CTL_SETCLE:
IO_ADDR_W |= MASK_CLE;
break;
case NAND_CTL_SETALE:
IO_ADDR_W |= MASK_ALE;
break;
case NAND_CTL_CLRNCE:
at91_set_gpio_value(AT91_PIN_PC14, 1);
break;
case NAND_CTL_SETNCE:
at91_set_gpio_value(AT91_PIN_PC14, 0);
break;
}
this->IO_ADDR_W = (void *) IO_ADDR_W;
}
static long at91gpio_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
{
int port_pin;
at91_gpio_ctl_s at91_gpio_ctl_arg;
if(copy_from_user(&at91_gpio_ctl_arg, (at91_gpio_ctl_s *)arg, sizeof(at91_gpio_ctl_s)) != 0 )
{
printk(KERN_INFO "error in copy_from_user!\n");
return -EFAULT;
}
//printk(KERN_INFO "******cmd****** : %d\n",cmd);
port_pin = get_port_pin(at91_gpio_ctl_arg.which_port, at91_gpio_ctl_arg.which_pin);
if(-1 == port_pin)
{
printk(KERN_INFO "get port and pin error!\n");
return -1;
}
switch(cmd)
{
case AT91GPIO_WRITE:
{
//printk(KERN_INFO "*******at91_gpio_write******\n");
at91_set_gpio_value(port_pin, at91_gpio_ctl_arg.value);
break;
}
case AT91GPIO_READ:
{
at91_gpio_ctl_arg.value = at91_get_gpio_value(port_pin);
//printk(KERN_INFO "====================\n");
//printk(KERN_INFO "gpio value : %d\n",at91_gpio_ctl_arg.value);
//printk(KERN_INFO "====================\n");
if(copy_to_user((at91_gpio_ctl_s *)arg, &at91_gpio_ctl_arg, sizeof(at91_gpio_ctl_s)) != 0)
{
return -EFAULT;
}
break;
}
case AT91GPIO_CTL:
{
//printk(KERN_INFO "*******at91_gpio_ctl******\n");
gpio_init(port_pin,at91_gpio_ctl_arg.inout);
break;
}
default:break;
}
return 0;
}
/*
* Enable NAND and detect card.
*/
static void at91_nand_enable(struct at91_nand_host *host)
{
unsigned int csa;
/* Setup Smart Media, first enable the address range of CS3 */
csa = at91_sys_read(AT91_EBI_CSA);
at91_sys_write(AT91_EBI_CSA, csa | AT91_EBI_CS3A_SMC_SMARTMEDIA);
/* set the bus interface characteristics */
at91_sys_write(AT91_SMC_CSR(3), AT91_SMC_ACSS_STD | AT91_SMC_DBW_8 | AT91_SMC_WSEN
| AT91_SMC_NWS_(5)
| AT91_SMC_TDF_(1)
| AT91_SMC_RWSETUP_(0) /* tDS Data Set up Time 30 - ns */
| AT91_SMC_RWHOLD_(1) /* tDH Data Hold Time 20 - ns */
);
if (host->board->enable_pin)
at91_set_gpio_value(host->board->enable_pin, 0);
}
static irqreturn_t txdtc_interrupt_handler(int irq, void *dev_id)
{
static int cycle = 0;
static char bits[10]; /* 11 send clock */
static char in_byte = 0x00;
int j=0;
clear_tc(TXD_CLOCK_CHN);
/* The data bit send cycle */
if( in_byte )
{
at91_set_gpio_value(AT91_PIN_PB4, bits[cycle]);
if(unlikely(STOP_BIT == cycle))
{
/* A byte data send over, tx_ring tail head on */
tx_ring.tail = (tx_ring.tail + 1) & (CIRC_BUF_SIZE - 1);
/* All the bit in a bytes send over */
in_byte = 0x00;
}
cycle++;
}
/* First cycle used to prepare the send data */
else if ( CIRC_CNT(tx_ring.head, tx_ring.tail, CIRC_BUF_SIZE) > 0 )
{
/* Start bit send low level*/
bits[START_BIT]=LOWLEVEL;
/* 8bits data in a byte */
for(j=0; j<8; j++)
bits[j+START_BIT+1]=(tx_ring.buf[tx_ring.tail]>>j) & 0x01;
/* Stop bit send high level*/
bits[STOP_BIT]=HIGHLEVEL;
/* Goes to next cycle start to send every bit in a bytes */
in_byte = 0x01;
cycle = START_BIT;
send_over = 0;
}