int miiphy_write(unsigned char addr, unsigned char reg, unsigned short value)
{
at91rm9200_EmacEnableMDIO (p_mac);
at91rm9200_EmacWritePhy (p_mac, reg, &value);
at91rm9200_EmacDisableMDIO (p_mac);
return 0;
}
/*
* Name:
* ste100p_DisableInterrupts
* Description:
* disables interrupts
* Arguments:
* p_mac - pointer to AT91S_EMAC struct
*/
void ste100p_DisableInterrupts (AT91PS_EMAC p_mac)
{
unsigned short IntValue;
unsigned int rep;
rep = 0;
at91rm9200_EmacEnableMDIO (p_mac);
/* Disable PHY Interrupts */
at91rm9200_EmacReadPhy (p_mac, STE100P_XIE_REG, &IntValue);
udelay(10000);
/* disable all interrypts from SE100P */
IntValue &= ~(STE100P_XIE_ANCE | STE100P_XIE_RFE | STE100P_XIE_LDE |
STE100P_XIE_ANAE | STE100P_XIE_PDFE | STE100P_XIE_ANPE | STE100P_XIE_REFE);
at91rm9200_EmacWritePhy (p_mac, STE100P_XIE_REG, &IntValue);
udelay(10000);
IntValue = 1;
do
{
at91rm9200_EmacReadPhy (p_mac, STE100P_XCSIIS_REG, &IntValue);
rep++;
} while (IntValue != 0 && rep < 100);
at91rm9200_EmacDisableMDIO (p_mac);
}
int miiphy_read(unsigned char addr, unsigned char reg, unsigned short * value)
{
at91rm9200_EmacEnableMDIO (p_mac);
at91rm9200_EmacReadPhy (p_mac, reg, value);
at91rm9200_EmacDisableMDIO (p_mac);
return 0;
}
int at91rm9200_miidev_write(char *devname, unsigned char addr,
unsigned char reg, unsigned short value)
{
at91rm9200_EmacEnableMDIO (p_mac);
at91rm9200_EmacWritePhy (p_mac, reg, &value);
at91rm9200_EmacDisableMDIO (p_mac);
return 0;
}
int at91rm9200_miidev_read(char *devname, unsigned char addr,
unsigned char reg, unsigned short * value)
{
at91rm9200_EmacEnableMDIO (p_mac);
at91rm9200_EmacReadPhy (p_mac, reg, value);
at91rm9200_EmacDisableMDIO (p_mac);
return 0;
}
/*
* Name:
* lxt972_IsPhyConnected
* Description:
* Reads the 2 PHY ID registers
* Arguments:
* p_mac - pointer to AT91S_EMAC struct
* Return value:
* TRUE - if id read successfully
* FALSE- if error
*/
unsigned int lxt972_IsPhyConnected (AT91PS_EMAC p_mac)
{
unsigned short Id1, Id2;
at91rm9200_EmacEnableMDIO (p_mac);
at91rm9200_EmacReadPhy(p_mac, PHY_PHYIDR1, &Id1);
at91rm9200_EmacReadPhy(p_mac, PHY_PHYIDR2, &Id2);
at91rm9200_EmacDisableMDIO (p_mac);
if ((Id1 == (0x0013)) && ((Id2 & 0xFFF0) == 0x78E0))
return TRUE;
return FALSE;
}
/*
* Name:
* lxt972_InitPhy
* Description:
* MAC starts checking its link by using parallel detection and
* Autonegotiation and the same is set in the MAC configuration registers
* Arguments:
* p_mac - pointer to struct AT91S_EMAC
* Return value:
* TRUE - if link status set succesfully
* FALSE - if link status not set
*/
UCHAR lxt972_InitPhy (AT91PS_EMAC p_mac)
{
UCHAR ret = TRUE;
at91rm9200_EmacEnableMDIO (p_mac);
if (!lxt972_GetLinkSpeed (p_mac)) {
/* Try another time */
ret = lxt972_GetLinkSpeed (p_mac);
}
/* Disable PHY Interrupts */
at91rm9200_EmacWritePhy (p_mac, PHY_LXT971_INT_ENABLE, 0);
at91rm9200_EmacDisableMDIO (p_mac);
return (ret);
}
/*
* Name:
* ste100p_IsPhyConnected
* Description:
* Reads the 2 PHY ID registers
* Arguments:
* p_mac - pointer to AT91S_EMAC struct
* Return value:
* TRUE - if id read successfully
* FALSE- if error
*/
unsigned int ste100p_IsPhyConnected (AT91PS_EMAC p_mac)
{
unsigned short Id1, Id2;
unsigned int result = FALSE;
unsigned int tries = 100;
at91rm9200_EmacEnableMDIO (p_mac);
udelay(10000);
do
{
Id1 = Id2 = 0;
udelay(10000);
at91rm9200_EmacReadPhy (p_mac, STE100P_PID1_REG, &Id1);
udelay(10000);
at91rm9200_EmacReadPhy (p_mac, STE100P_PID2_REG, &Id2);
Id2 = (Id2 & STE100P_PID2_PHYID_MASK) >> 6;
if ((Id1 == STE100P_PID1_PHYID_VAL) && (Id2 == STE100P_PID2_PHYID_VAL))
result = TRUE;
tries--;
} while ((!result) && (tries > 0));
if (tries == 0)
{
#ifdef DEBUG_ETHER
printf("Exceeded maximum number of tries while checking if PHY is connected (PID1: 0x%4x, PID2: 0x%4x)\r\n", Id1, Id2);
#endif
return FALSE;
}
at91rm9200_EmacDisableMDIO (p_mac);
#ifdef DEBUG_ETHER
printf ("ste100p id1[0x%02x] id2[0x%02x]\r\n", Id1, Id2);
#endif
return result;
}
unsigned int ste100p_Isolate (AT91PS_EMAC p_mac)
{
unsigned int result = FALSE;
unsigned short IntValue;
at91rm9200_EmacEnableMDIO (p_mac);
udelay(10000);
at91rm9200_EmacReadPhy (p_mac, STE100P_XCR_REG, &IntValue);
IntValue |= STE100P_XCR_ISOLATE ;//| STE100P_XCR_PWRDN;
//IntValue &= ~STE100P_XCR_RESET;
//IntValue &= ~STE100P_XCR_AN;
result = at91rm9200_EmacWritePhy (p_mac, STE100P_XCR_REG, &IntValue);
udelay(10000);
//Isolate is latch so we need to read once more the register
at91rm9200_EmacReadPhy (p_mac, STE100P_XCR_REG, &IntValue);
at91rm9200_EmacDisableMDIO (p_mac);
#ifdef DEBUG_ETHER
printf("ste100p_Isolate [%d]\n", result);
#endif
return result;
}
/*
* Name:
* ste100p_InitPhy
* Description:
* MAC starts checking its link by using parallel detection and
* Autonegotiation and the same is set in the MAC configuration registers
* Arguments:
* p_mac - pointer to struct AT91S_EMAC
* Return value:
* TRUE - if link status set succesfully
* FALSE - if link status not set
*/
UCHAR ste100p_InitPhy (AT91PS_EMAC p_mac)
{
UCHAR ret = FALSE;
unsigned short IntValue;
int aneg_status;
PhyReset(p_mac);
at91rm9200_EmacEnableMDIO (p_mac);
ste100p_Deisolate(p_mac);
at91rm9200_EmacDisableMDIO (p_mac);
#if 1
at91rm9200_EmacEnableMDIO (p_mac);
ste100p_WaitForLink(p_mac, 500 /* timeout in ms */);
ret = ste100p_GetLinkSpeed (p_mac);
if (!ret)
{
ret = ste100p_AutoNegotiate(p_mac, &aneg_status);
#ifdef DEBUG_ETHER
if (aneg_status)
{
printf("link speed autonegotiated (%d): ", ret);
ret = ste100p_GetLinkSpeed (p_mac);
}
else
printf("auto-negotiation failed\n");
#endif //DEBUG_ETHER
}
/* Disable PHY Interrupts */
at91rm9200_EmacReadPhy (p_mac, STE100P_XIE_REG, &IntValue);
udelay(1000);
/* disable all interrypts from STE100P */
IntValue &= ~(STE100P_XIE_ANCE | STE100P_XIE_RFE | STE100P_XIE_LDE |
STE100P_XIE_ANAE | STE100P_XIE_PDFE | STE100P_XIE_ANPE | STE100P_XIE_REFE);
at91rm9200_EmacWritePhy (p_mac, STE100P_XIE_REG, &IntValue);
udelay(10000);
at91rm9200_EmacDisableMDIO (p_mac);
udelay(1000);
#endif
#ifdef DEBUG_ETHER
printf("ste100p InitPhy [");
if (ret)
printf("OK]\n");
else
printf("FAILED]\n");
#endif //DEBUG_ETHER
return (ret);
}
static void PhyReset(AT91PS_EMAC p_mac)
{
unsigned short IntValue;
unsigned int timeout;
#ifdef DEBUG_ETHER
printf("ste100p PhyReset \n");
#endif
at91rm9200_EmacEnableMDIO (p_mac);
// first software reset the STE100P
at91rm9200_EmacReadPhy (p_mac, STE100P_XCR_REG, &IntValue);
udelay(1000);
IntValue |= STE100P_XCR_RESET;
at91rm9200_EmacWritePhy (p_mac, STE100P_XCR_REG, &IntValue);
udelay(10000);
timeout = 100;
while (--timeout)
{
at91rm9200_EmacReadPhy (p_mac, STE100P_XCR_REG, &IntValue);
if ((IntValue & STE100P_XCR_RESET) != STE100P_XCR_RESET)
{
#ifdef DEBUG_ETHER
printf("PHY Reset OK\n");
#endif
break;
}
udelay(1000);
}
IntValue = STE100P_ANA_FC | STE100P_ANA_TXF | STE100P_ANA_TXH |
STE100P_ANA_10F | STE100P_ANA_10H;
at91rm9200_EmacWritePhy (p_mac, STE100P_ANA_REG, &IntValue);
//default configuration
#ifdef CONFIG_STE100P_OVERRIDE_HARDWARE
IntValue = STE100P_100CTR_ENDCR | STE100P_100CTR_ENRZI | STE100P_100CTR_EN4B5B;
IntValue &= ~(STE100P_100CTR_DISRER);
IntValue &= ~(STE100P_100CTR_ISOTX);
IntValue &= ~(STE100P_100CTR_DISMLT);
IntValue &= ~(STE100P_100CTR_DISCRM);
at91rm9200_EmacWritePhy (p_mac, STE100P_100CTR_REG, &IntValue);
#endif //CONFIG_STE100P_OVERRIDE_HARDWARE
/* Disable PHY Interrupts */
at91rm9200_EmacReadPhy (p_mac, STE100P_XIE_REG, &IntValue);
udelay(10000);
/* disable all interrupts from STE100P */
IntValue &= ~(STE100P_XIE_ANCE | STE100P_XIE_RFE | STE100P_XIE_LDE |
STE100P_XIE_ANAE | STE100P_XIE_PDFE | STE100P_XIE_ANPE | STE100P_XIE_REFE);
at91rm9200_EmacWritePhy (p_mac, STE100P_XIE_REG, &IntValue);
udelay(10000);
at91rm9200_EmacReadPhy (p_mac, STE100P_XCR_REG, &IntValue);
IntValue |= STE100P_XCR_AN | STE100P_XCR_RSTRT_AN;
at91rm9200_EmacWritePhy (p_mac, STE100P_XCR_REG, &IntValue);
at91rm9200_EmacDisableMDIO (p_mac);
}
