/*
* Set up both clocksource and clockevent support.
*/
static void __init at91sam926x_pit_init(void)
{
unsigned long pit_rate;
unsigned bits;
printk (KERN_ALERT "petworm: pit init.\n");
/*
* Use our actual MCK to figure out how many MCK/16 ticks per
* 1/HZ period (instead of a compile-time constant LATCH).
*/
pit_rate = clk_get_rate(clk_get(NULL, "mck")) / 16;
pit_cycle = (pit_rate + HZ/2) / HZ;
WARN_ON(((pit_cycle - 1) & ~AT91_PIT_PIV) != 0);
/* Initialize and enable the timer */
at91sam926x_pit_reset();
/*
* Register clocksource. The high order bits of PIV are unused,
* so this isn't a 32-bit counter unless we get clockevent irqs.
*/
pit_clk.mult = clocksource_hz2mult(pit_rate, pit_clk.shift);
bits = 12 /* PICNT */ + ilog2(pit_cycle) /* PIV */;
pit_clk.mask = CLOCKSOURCE_MASK(bits);
clocksource_register(&pit_clk);
/* Set up irq handler */
setup_irq(AT91_ID_SYS, &at91sam926x_pit_irq);
/* Set up and register clockevents */
pit_clkevt.mult = div_sc(pit_rate, NSEC_PER_SEC, pit_clkevt.shift);
clockevents_register_device(&pit_clkevt);
}
/*
* Set up both clocksource and clockevent support.
*/
static void at91sam926x_pit_init(void)
{
rt_uint32_t pit_rate;
rt_uint32_t bits;
/*
* Use our actual MCK to figure out how many MCK/16 ticks per
* 1/HZ period (instead of a compile-time constant LATCH).
*/
pit_rate = clk_get_rate(clk_get("mck")) / 16;
rt_kprintf("pit_rate=%dHZ\n", pit_rate);
pit_cycle = (pit_rate + RT_TICK_PER_SECOND/2) / RT_TICK_PER_SECOND;
/* Initialize and enable the timer */
at91sam926x_pit_reset();
}
/*
* Set up both clocksource and clockevent support.
*/
void __init at91sam926x_pit_init(void)
{
unsigned long pit_rate;
unsigned bits;
int ret;
mck = ERR_PTR(-ENOENT);
/* For device tree enabled device: initialize here */
of_at91sam926x_pit_init();
/*
* Use our actual MCK to figure out how many MCK/16 ticks per
* 1/HZ period (instead of a compile-time constant LATCH).
*/
if (IS_ERR(mck))
mck = clk_get(NULL, "mck");
if (IS_ERR(mck))
panic("AT91: PIT: Unable to get mck clk\n");
pit_rate = clk_get_rate(mck) / 16;
pit_cycle = (pit_rate + HZ/2) / HZ;
WARN_ON(((pit_cycle - 1) & ~AT91_PIT_PIV) != 0);
/* Initialize and enable the timer */
at91sam926x_pit_reset();
/*
* Register clocksource. The high order bits of PIV are unused,
* so this isn't a 32-bit counter unless we get clockevent irqs.
*/
bits = 12 /* PICNT */ + ilog2(pit_cycle) /* PIV */;
pit_clk.mask = CLOCKSOURCE_MASK(bits);
clocksource_register_hz(&pit_clk, pit_rate);
/* Set up irq handler */
ret = setup_irq(at91sam926x_pit_irq.irq, &at91sam926x_pit_irq);
if (ret)
pr_crit("AT91: PIT: Unable to setup IRQ\n");
/* Set up and register clockevents */
pit_clkevt.mult = div_sc(pit_rate, NSEC_PER_SEC, pit_clkevt.shift);
pit_clkevt.cpumask = cpumask_of(0);
clockevents_register_device(&pit_clkevt);
}
/*
* Set up both clocksource and clockevent support.
*/
static void __init at91sam926x_pit_init(void)
{
unsigned long pit_rate;
unsigned bits;
/*
* Use our actual MCK to figure out how many MCK/16 ticks per
* 1/HZ period (instead of a compile-time constant LATCH).
*/
pit_rate = clk_get_rate(clk_get(NULL, "mck")) / 16;
pit_cycle = (pit_rate + HZ/2) / HZ;
WARN_ON(((pit_cycle - 1) & ~AT91_PIT_PIV) != 0);
/* Initialize and enable the timer */
at91sam926x_pit_reset();
/*
* Register clocksource. The high order bits of PIV are unused,
* so this isn't a 32-bit counter unless we get clockevent irqs.
*/
<<<<<<< HEAD
static void at91sam926x_pit_resume(struct clock_event_device *cedev)
{
at91sam926x_pit_reset();
}
