int ata_usbchannel_end_transaction(struct ata_request *request) { if (atausbdebug > 1) device_printf(request->dev, "end_transaction %s\n", ata_cmd2str(request)); /* XXX SOS convert the request from the format used, only BBB for now*/ /* ATA/ATAPI IDENTIFY needs special treatment */ if ((request->flags & ATA_R_ATAPI) && (request->u.atapi.ccb[0] == ATAPI_INQUIRY)) { struct ata_device *atadev = device_get_softc(request->dev); struct atapi_inquiry *inquiry = (struct atapi_inquiry *)request->data; u_int16_t *ptr; /* convert inquiry data into simple ata_param like format */ atadev->param.config = ATA_PROTO_ATAPI | ATA_PROTO_ATAPI_12; atadev->param.config |= (inquiry->device_type & 0x1f) << 8; bzero(atadev->param.model, sizeof(atadev->param.model)); strncpy(atadev->param.model, inquiry->vendor, 8); strcpy(atadev->param.model, " "); strncpy(atadev->param.model, inquiry->product, 16); ptr = (u_int16_t*)(atadev->param.model + sizeof(atadev->param.model)); while (--ptr >= (u_int16_t*)atadev->param.model) *ptr = ntohs(*ptr); strncpy(atadev->param.revision, inquiry->revision, 4); ptr=(u_int16_t*)(atadev->param.revision+sizeof(atadev->param.revision)); while (--ptr >= (u_int16_t*)atadev->param.revision) *ptr = ntohs(*ptr); request->result = 0; } return ATA_OP_FINISHED; }
int ata_usbchannel_begin_transaction(struct ata_request *request) { struct atausb_softc *sc = device_get_softc(device_get_parent(request->parent)); if (atausbdebug > 1) device_printf(request->dev, "begin_transaction %s\n", ata_cmd2str(request)); /* sanity just in case */ if (sc->state != ATAUSB_S_IDLE) { kprintf("begin is busy (%d)\n", sc->state); request->result = EBUSY; return ATA_OP_FINISHED; } /* XXX SOS convert the request into the format used, only BBB for now*/ sc->ata_request = request; /* ATA/ATAPI IDENTIFY needs special treatment */ if (!(request->flags & ATA_R_ATAPI)) { if (request->u.ata.command != ATA_ATAPI_IDENTIFY) { device_printf(request->dev,"%s unsupported\n",ata_cmd2str(request)); request->result = EIO; return ATA_OP_FINISHED; } request->flags |= ATA_R_ATAPI; bzero(request->u.atapi.ccb, 16); request->u.atapi.ccb[0] = ATAPI_INQUIRY; request->u.atapi.ccb[4] = 255; /* sizeof(struct atapi_inquiry); */ request->data += 256; /* arbitrary offset into ata_param */ request->bytecount = 255; /* sizeof(struct atapi_inquiry); */ } return atausb_bbb_start(request); }
/* must be called with ATA channel locked and state_mtx held */ int ata_begin_transaction(struct ata_request *request) { struct ata_channel *ch = device_get_softc(request->parent); int dummy, error; ATA_DEBUG_RQ(request, "begin transaction"); /* disable ATAPI DMA writes if HW doesn't support it */ if ((ch->flags & ATA_NO_ATAPI_DMA) && (request->flags & ATA_R_ATAPI) == ATA_R_ATAPI) request->flags &= ~ATA_R_DMA; if ((ch->flags & ATA_ATAPI_DMA_RO) && ((request->flags & (ATA_R_ATAPI | ATA_R_DMA | ATA_R_WRITE)) == (ATA_R_ATAPI | ATA_R_DMA | ATA_R_WRITE))) request->flags &= ~ATA_R_DMA; switch (request->flags & (ATA_R_ATAPI | ATA_R_DMA)) { /* ATA PIO data transfer and control commands */ default: { /* record command direction here as our request might be gone later */ int write = (request->flags & ATA_R_WRITE); /* issue command */ if (ch->hw.command(request)) { device_printf(request->parent, "error issuing %s command\n", ata_cmd2str(request)); request->result = EIO; goto begin_finished; } /* device reset doesn't interrupt */ if (request->u.ata.command == ATA_DEVICE_RESET) { int timeout = 1000000; do { DELAY(10); request->status = ATA_IDX_INB(ch, ATA_STATUS); } while (request->status & ATA_S_BUSY && timeout--); if (request->status & ATA_S_ERROR) request->error = ATA_IDX_INB(ch, ATA_ERROR); goto begin_finished; } /* if write command output the data */ if (write) { if (ata_wait(ch, request->unit, (ATA_S_READY | ATA_S_DRQ)) < 0) { device_printf(request->parent, "timeout waiting for write DRQ\n"); request->result = EIO; goto begin_finished; } ata_pio_write(request, request->transfersize); } } goto begin_continue; /* ATA DMA data transfer commands */ case ATA_R_DMA: /* check sanity, setup SG list and DMA engine */ if ((error = ch->dma.load(request, NULL, &dummy))) { device_printf(request->parent, "setting up DMA failed\n"); request->result = error; goto begin_finished; } /* start DMA engine if necessary */ if ((ch->flags & ATA_DMA_BEFORE_CMD) && ch->dma.start && ch->dma.start(request)) { device_printf(request->parent, "error starting DMA\n"); request->result = EIO; goto begin_finished; } /* issue command */ if (ch->hw.command(request)) { device_printf(request->parent, "error issuing %s command\n", ata_cmd2str(request)); request->result = EIO; goto begin_finished; } /* start DMA engine */ if (!(ch->flags & ATA_DMA_BEFORE_CMD) && ch->dma.start && ch->dma.start(request)) { device_printf(request->parent, "error starting DMA\n"); request->result = EIO; goto begin_finished; } goto begin_continue; /* ATAPI PIO commands */ case ATA_R_ATAPI: /* is this just a POLL DSC command ? */ if (request->u.atapi.ccb[0] == ATAPI_POLL_DSC) { ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(request->unit)); DELAY(10); if (!(ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_DSC)) request->result = EBUSY; goto begin_finished; } /* start ATAPI operation */ if (ch->hw.command(request)) { device_printf(request->parent, "error issuing ATA PACKET command\n"); request->result = EIO; goto begin_finished; } goto begin_continue; /* ATAPI DMA commands */ case ATA_R_ATAPI|ATA_R_DMA: /* is this just a POLL DSC command ? */ if (request->u.atapi.ccb[0] == ATAPI_POLL_DSC) { ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(request->unit)); DELAY(10); if (!(ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_DSC)) request->result = EBUSY; goto begin_finished; } /* check sanity, setup SG list and DMA engine */ if ((error = ch->dma.load(request, NULL, &dummy))) { device_printf(request->parent, "setting up DMA failed\n"); request->result = error; goto begin_finished; } /* start ATAPI operation */ if (ch->hw.command(request)) { device_printf(request->parent, "error issuing ATA PACKET command\n"); request->result = EIO; goto begin_finished; } /* start DMA engine */ if (ch->dma.start && ch->dma.start(request)) { request->result = EIO; goto begin_finished; } goto begin_continue; } /* NOT REACHED */ printf("ata_begin_transaction OOPS!!!\n"); begin_finished: if (ch->dma.unload) { ch->dma.unload(request); } return ATA_OP_FINISHED; begin_continue: callout_reset(&request->callout, request->timeout * hz, (timeout_t*)ata_timeout, request); return ATA_OP_CONTINUES; }
/* must be called with ATA channel locked and state_mtx held */ int ata_end_transaction(struct ata_request *request) { struct ata_channel *ch = device_get_softc(request->parent); int length; ATA_DEBUG_RQ(request, "end transaction"); /* clear interrupt and get status */ request->status = ATA_IDX_INB(ch, ATA_STATUS); switch (request->flags & (ATA_R_ATAPI | ATA_R_DMA | ATA_R_CONTROL)) { /* ATA PIO data transfer and control commands */ default: /* on timeouts we have no data or anything so just return */ if (request->flags & ATA_R_TIMEOUT) goto end_finished; /* on control commands read back registers to the request struct */ if (request->flags & ATA_R_CONTROL) { ch->hw.tf_read(request); } /* if we got an error we are done with the HW */ if (request->status & ATA_S_ERROR) { request->error = ATA_IDX_INB(ch, ATA_ERROR); goto end_finished; } /* are we moving data ? */ if (request->flags & (ATA_R_READ | ATA_R_WRITE)) { /* if read data get it */ if (request->flags & ATA_R_READ) { int flags = ATA_S_DRQ; if (request->u.ata.command != ATA_ATAPI_IDENTIFY) flags |= ATA_S_READY; if (ata_wait(ch, request->unit, flags) < 0) { device_printf(request->parent, "timeout waiting for read DRQ\n"); request->result = EIO; goto end_finished; } ata_pio_read(request, request->transfersize); } /* update how far we've gotten */ request->donecount += request->transfersize; /* do we need a scoop more ? */ if (request->bytecount > request->donecount) { /* set this transfer size according to HW capabilities */ request->transfersize = min((request->bytecount - request->donecount), request->transfersize); /* if data write command, output the data */ if (request->flags & ATA_R_WRITE) { /* if we get an error here we are done with the HW */ if (ata_wait(ch, request->unit, (ATA_S_READY | ATA_S_DRQ)) < 0) { device_printf(request->parent, "timeout waiting for write DRQ\n"); request->status = ATA_IDX_INB(ch, ATA_STATUS); goto end_finished; } /* output data and return waiting for new interrupt */ ata_pio_write(request, request->transfersize); goto end_continue; } /* if data read command, return & wait for interrupt */ if (request->flags & ATA_R_READ) goto end_continue; } } /* done with HW */ goto end_finished; /* ATA DMA data transfer commands */ case ATA_R_DMA: /* stop DMA engine and get status */ if (ch->dma.stop) request->dma->status = ch->dma.stop(request); /* did we get error or data */ if (request->status & ATA_S_ERROR) request->error = ATA_IDX_INB(ch, ATA_ERROR); else if (request->dma->status & ATA_BMSTAT_ERROR) request->status |= ATA_S_ERROR; else if (!(request->flags & ATA_R_TIMEOUT)) request->donecount = request->bytecount; /* release SG list etc */ ch->dma.unload(request); /* done with HW */ goto end_finished; /* ATAPI PIO commands */ case ATA_R_ATAPI: length = ATA_IDX_INB(ch, ATA_CYL_LSB)|(ATA_IDX_INB(ch, ATA_CYL_MSB)<<8); /* on timeouts we have no data or anything so just return */ if (request->flags & ATA_R_TIMEOUT) goto end_finished; switch ((ATA_IDX_INB(ch, ATA_IREASON) & (ATA_I_CMD | ATA_I_IN)) | (request->status & ATA_S_DRQ)) { case ATAPI_P_CMDOUT: /* this seems to be needed for some (slow) devices */ DELAY(10); if (!(request->status & ATA_S_DRQ)) { device_printf(request->parent, "command interrupt without DRQ\n"); request->status = ATA_S_ERROR; goto end_finished; } ATA_IDX_OUTSW_STRM(ch, ATA_DATA, (int16_t *)request->u.atapi.ccb, (request->flags & ATA_R_ATAPI16) ? 8 : 6); /* return wait for interrupt */ goto end_continue; case ATAPI_P_WRITE: if (request->flags & ATA_R_READ) { request->status = ATA_S_ERROR; device_printf(request->parent, "%s trying to write on read buffer\n", ata_cmd2str(request)); goto end_finished; } ata_pio_write(request, length); request->donecount += length; /* set next transfer size according to HW capabilities */ request->transfersize = min((request->bytecount-request->donecount), request->transfersize); /* return wait for interrupt */ goto end_continue; case ATAPI_P_READ: if (request->flags & ATA_R_WRITE) { request->status = ATA_S_ERROR; device_printf(request->parent, "%s trying to read on write buffer\n", ata_cmd2str(request)); goto end_finished; } ata_pio_read(request, length); request->donecount += length; /* set next transfer size according to HW capabilities */ request->transfersize = min((request->bytecount-request->donecount), request->transfersize); /* return wait for interrupt */ goto end_continue; case ATAPI_P_DONEDRQ: device_printf(request->parent, "WARNING - %s DONEDRQ non conformant device\n", ata_cmd2str(request)); if (request->flags & ATA_R_READ) { ata_pio_read(request, length); request->donecount += length; } else if (request->flags & ATA_R_WRITE) { ata_pio_write(request, length); request->donecount += length; } else request->status = ATA_S_ERROR; /* FALLTHROUGH */ case ATAPI_P_ABORT: case ATAPI_P_DONE: if (request->status & (ATA_S_ERROR | ATA_S_DWF)) request->error = ATA_IDX_INB(ch, ATA_ERROR); goto end_finished; default: device_printf(request->parent, "unknown transfer phase\n"); request->status = ATA_S_ERROR; } /* done with HW */ goto end_finished; /* ATAPI DMA commands */ case ATA_R_ATAPI|ATA_R_DMA: /* stop DMA engine and get status */ if (ch->dma.stop) request->dma->status = ch->dma.stop(request); /* did we get error or data */ if (request->status & (ATA_S_ERROR | ATA_S_DWF)) request->error = ATA_IDX_INB(ch, ATA_ERROR); else if (request->dma->status & ATA_BMSTAT_ERROR) request->status |= ATA_S_ERROR; else if (!(request->flags & ATA_R_TIMEOUT)) request->donecount = request->bytecount; /* release SG list etc */ ch->dma.unload(request); /* done with HW */ goto end_finished; } /* NOT REACHED */ printf("ata_end_transaction OOPS!!\n"); end_finished: callout_stop(&request->callout); return ATA_OP_FINISHED; end_continue: return ATA_OP_CONTINUES; }
int ata_reinit(device_t dev) { struct ata_channel *ch = device_get_softc(dev); struct ata_request *request; device_t *children; int nchildren, i; /* check that we have a valid channel to reinit */ if (!ch || !ch->r_irq) return ENXIO; if (bootverbose) device_printf(dev, "reiniting channel ..\n"); /* poll for locking the channel */ while (ATA_LOCKING(dev, ATA_LF_LOCK) != ch->unit) pause("atarini", 1); /* catch eventual request in ch->running */ mtx_lock(&ch->state_mtx); if ((request = ch->running)) callout_stop(&request->callout); ch->running = NULL; /* unconditionally grap the channel lock */ ch->state |= ATA_STALL_QUEUE; mtx_unlock(&ch->state_mtx); /* reset the controller HW, the channel and device(s) */ ATA_RESET(dev); /* reinit the children and delete any that fails */ if (!device_get_children(dev, &children, &nchildren)) { mtx_lock(&Giant); /* newbus suckage it needs Giant */ for (i = 0; i < nchildren; i++) { /* did any children go missing ? */ if (children[i] && device_is_attached(children[i]) && ATA_REINIT(children[i])) { /* * if we had a running request and its device matches * this child we need to inform the request that the * device is gone. */ if (request && request->dev == children[i]) { request->result = ENXIO; device_printf(request->dev, "FAILURE - device detached\n"); /* if not timeout finish request here */ if (!(request->flags & ATA_R_TIMEOUT)) ata_finish(request); request = NULL; } device_delete_child(dev, children[i]); } } free(children, M_TEMP); mtx_unlock(&Giant); /* newbus suckage dealt with, release Giant */ } /* if we still have a good request put it on the queue again */ if (request && !(request->flags & ATA_R_TIMEOUT)) { device_printf(request->dev, "WARNING - %s requeued due to channel reset", ata_cmd2str(request)); if (!(request->flags & (ATA_R_ATAPI | ATA_R_CONTROL))) printf(" LBA=%ju", request->u.ata.lba); printf("\n"); request->flags |= ATA_R_REQUEUE; ata_queue_request(request); } /* we're done release the channel for new work */ mtx_lock(&ch->state_mtx); ch->state = ATA_IDLE; mtx_unlock(&ch->state_mtx); ATA_LOCKING(dev, ATA_LF_UNLOCK); if (bootverbose) device_printf(dev, "reinit done ..\n"); /* kick off requests on the queue */ ata_start(dev); return 0; }
static int ata_siiprb_end_transaction(struct ata_request *request) { struct ata_pci_controller *ctlr=device_get_softc(device_get_parent(request->parent)); struct ata_channel *ch = device_get_softc(request->parent); struct ata_siiprb_command *prb; int offset = ch->unit * 0x2000; int error, timeout; /* kill the timeout */ callout_stop(&request->callout); bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, BUS_DMASYNC_POSTWRITE); prb = (struct ata_siiprb_command *) ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + offset); /* any controller errors flagged ? */ if ((error = ATA_INL(ctlr->r_res2, 0x1024 + offset))) { if (bootverbose) printf("ata_siiprb_end_transaction %s error=%08x\n", ata_cmd2str(request), error); /* if device error status get details */ if (error == 1 || error == 2) { request->status = prb->fis[2]; if (request->status & ATA_S_ERROR) request->error = prb->fis[3]; } /* SOS XXX handle other controller errors here */ /* initialize port */ ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000004); /* poll for port ready */ for (timeout = 0; timeout < 1000; timeout++) { DELAY(1000); if (ATA_INL(ctlr->r_res2, 0x1008 + offset) & 0x00040000) break; } if (bootverbose) { if (timeout >= 1000) device_printf(ch->dev, "port initialize timeout\n"); else device_printf(ch->dev, "port initialize time=%dms\n", timeout); } } /* on control commands read back registers to the request struct */ if (request->flags & ATA_R_CONTROL) { request->u.ata.count = prb->fis[12] | ((u_int16_t)prb->fis[13] << 8); request->u.ata.lba = prb->fis[4] | ((u_int64_t)prb->fis[5] << 8) | ((u_int64_t)prb->fis[6] << 16); if (request->flags & ATA_R_48BIT) request->u.ata.lba |= ((u_int64_t)prb->fis[8] << 24) | ((u_int64_t)prb->fis[9] << 32) | ((u_int64_t)prb->fis[10] << 40); else request->u.ata.lba |= ((u_int64_t)(prb->fis[7] & 0x0f) << 24); } /* update progress */ if (!(request->status & ATA_S_ERROR) && !(request->flags & ATA_R_TIMEOUT)) { if (request->flags & ATA_R_READ) request->donecount = le32toh(prb->transfer_count); else request->donecount = request->bytecount; } /* release SG list etc */ ch->dma.unload(request); return ATA_OP_FINISHED; }
static void ata_interrupt(void *data) { struct ata_channel *ch = (struct ata_channel *)data; struct ata_request *request = ch->running; int length; /* ignore this interrupt if there is no running request */ if (!request) { if (ATA_LOCK_CH(ch, ATA_CONTROL)) { u_int8_t status = ATA_IDX_INB(ch, ATA_STATUS); u_int8_t error = ATA_IDX_INB(ch, ATA_ERROR); if (bootverbose) ata_printf(ch, -1, "spurious interrupt - status=0x%02x error=0x%02x\n", status, error); ATA_UNLOCK_CH(ch); } else { if (bootverbose) ata_printf(ch, -1, "spurious interrupt - channel busy\n"); } return; } ATA_DEBUG_RQ(request, "interrupt"); /* ignore interrupt if device is busy */ if (!(request->flags & ATA_R_TIMEOUT) && ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_BUSY) { DELAY(100); if (!(ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_DRQ)) return; } ATA_DEBUG_RQ(request, "interrupt accepted"); /* clear interrupt and get status */ request->status = ATA_IDX_INB(ch, ATA_STATUS); request->flags |= ATA_R_INTR_SEEN; switch (request->flags & (ATA_R_ATAPI | ATA_R_DMA | ATA_R_CONTROL)) { /* ATA PIO data transfer and control commands */ default: /* on control commands read back registers to the request struct */ if (request->flags & ATA_R_CONTROL) { request->u.ata.count = ATA_IDX_INB(ch, ATA_COUNT); request->u.ata.lba = ATA_IDX_INB(ch, ATA_SECTOR) | (ATA_IDX_INB(ch, ATA_CYL_LSB) << 8) | (ATA_IDX_INB(ch, ATA_CYL_MSB) << 16); } /* if we got an error we are done with the HW */ if (request->status & ATA_S_ERROR) { request->error = ATA_IDX_INB(ch, ATA_ERROR); break; } /* are we moving data ? */ if (request->flags & (ATA_R_READ | ATA_R_WRITE)) { /* if read data get it */ if (request->flags & ATA_R_READ) ata_pio_read(request, request->transfersize); /* update how far we've gotten */ request->donecount += request->transfersize; /* do we need a scoop more ? */ if (request->bytecount > request->donecount) { /* set this transfer size according to HW capabilities */ request->transfersize = min((request->bytecount - request->donecount), request->transfersize); /* clear interrupt seen flag as we need to wait again */ request->flags &= ~ATA_R_INTR_SEEN; /* if data write command, output the data */ if (request->flags & ATA_R_WRITE) { /* if we get an error here we are done with the HW */ if (ata_wait(request->device, (ATA_S_READY | ATA_S_DSC | ATA_S_DRQ)) < 0) { ata_prtdev(request->device, "timeout waiting for write DRQ"); request->status = ATA_IDX_INB(ch, ATA_STATUS); break; } /* output data and return waiting for new interrupt */ ata_pio_write(request, request->transfersize); return; } /* if data read command, return & wait for interrupt */ if (request->flags & ATA_R_READ) return; } } /* done with HW */ break; /* ATA DMA data transfer commands */ case ATA_R_DMA: /* stop DMA engine and get status */ request->dmastat = ch->dma->stop(ch); /* did we get error or data */ if (request->status & ATA_S_ERROR) request->error = ATA_IDX_INB(ch, ATA_ERROR); else if (request->dmastat & ATA_BMSTAT_ERROR) request->status |= ATA_S_ERROR; else request->donecount = request->bytecount; /* release SG list etc */ ch->dma->unload(ch); /* done with HW */ break; /* ATAPI PIO commands */ case ATA_R_ATAPI: length = ATA_IDX_INB(ch, ATA_CYL_LSB)|(ATA_IDX_INB(ch, ATA_CYL_MSB)<<8); switch ((ATA_IDX_INB(ch, ATA_IREASON) & (ATA_I_CMD | ATA_I_IN)) | (request->status & ATA_S_DRQ)) { case ATAPI_P_CMDOUT: /* this seems to be needed for some (slow) devices */ DELAY(10); if (!(request->status & ATA_S_DRQ)) { ata_prtdev(request->device, "command interrupt without DRQ\n"); request->status = ATA_S_ERROR; break; } ATA_IDX_OUTSW_STRM(ch, ATA_DATA, (int16_t *)request->u.atapi.ccb, (request->device->param->config & ATA_PROTO_MASK)== ATA_PROTO_ATAPI_12 ? 6 : 8); /* return wait for interrupt */ return; case ATAPI_P_WRITE: if (request->flags & ATA_R_READ) { request->status = ATA_S_ERROR; ata_prtdev(request->device, "%s trying to write on read buffer\n", ata_cmd2str(request)); break; } ata_pio_write(request, length); request->donecount += length; /* set next transfer size according to HW capabilities */ request->transfersize = min((request->bytecount-request->donecount), request->transfersize); /* return wait for interrupt */ return; case ATAPI_P_READ: if (request->flags & ATA_R_WRITE) { request->status = ATA_S_ERROR; ata_prtdev(request->device, "%s trying to read on write buffer\n", ata_cmd2str(request)); break; } ata_pio_read(request, length); request->donecount += length; /* set next transfer size according to HW capabilities */ request->transfersize = min((request->bytecount-request->donecount), request->transfersize); /* return wait for interrupt */ return; case ATAPI_P_DONEDRQ: ata_prtdev(request->device, "WARNING - %s DONEDRQ non conformant device\n", ata_cmd2str(request)); if (request->flags & ATA_R_READ) { ata_pio_read(request, length); request->donecount += length; } else if (request->flags & ATA_R_WRITE) { ata_pio_write(request, length); request->donecount += length; } else request->status = ATA_S_ERROR; /* FALLTHROUGH */ case ATAPI_P_ABORT: case ATAPI_P_DONE: if (request->status & (ATA_S_ERROR | ATA_S_DWF)) request->error = ATA_IDX_INB(ch, ATA_ERROR); break; default: ata_prtdev(request->device, "unknown transfer phase\n"); request->status = ATA_S_ERROR; } /* done with HW */ break; /* ATAPI DMA commands */ case ATA_R_ATAPI|ATA_R_DMA: /* stop the engine and get engine status */ request->dmastat = ch->dma->stop(ch); /* did we get error or data */ if (request->status & (ATA_S_ERROR | ATA_S_DWF)) request->error = ATA_IDX_INB(ch, ATA_ERROR); else if (request->dmastat & ATA_BMSTAT_ERROR) request->status |= ATA_S_ERROR; else request->donecount = request->bytecount; /* release SG list etc */ ch->dma->unload(ch); /* done with HW */ break; } /* if we timed out the unlocking of the ATA channel is done later */ if (!(request->flags & ATA_R_TIMEOUT)) { ch->running = NULL; ATA_UNLOCK_CH(ch); ch->locking(ch, ATA_LF_UNLOCK); } /* schedule completition for this request */ ata_finish(request); }
/* must be called with ATA channel locked */ static int ata_begin_transaction(struct ata_request *request) { struct ata_channel *ch = request->device->channel; /* safetybelt for HW that went away */ if (!request->device->param || request->device->channel->flags&ATA_HWGONE) { request->retries = 0; request->result = ENXIO; return ATA_OP_FINISHED; } ATA_DEBUG_RQ(request, "begin transaction"); /* disable ATAPI DMA writes if HW doesn't support it */ if ((ch->flags & ATA_ATAPI_DMA_RO) && ((request->flags & (ATA_R_ATAPI | ATA_R_DMA | ATA_R_WRITE)) == (ATA_R_ATAPI | ATA_R_DMA | ATA_R_WRITE))) request->flags &= ~ATA_R_DMA; switch (request->flags & (ATA_R_ATAPI | ATA_R_DMA)) { /* ATA PIO data transfer and control commands */ default: { /* record command direction here as our request might be gone later */ int write = (request->flags & ATA_R_WRITE); /* issue command */ if (ch->hw.command(request->device, request->u.ata.command, request->u.ata.lba, request->u.ata.count, request->u.ata.feature)) { ata_prtdev(request->device, "error issueing %s command\n", ata_cmd2str(request)); request->result = EIO; break; } /* device reset doesn't interrupt */ if (request->u.ata.command == ATA_ATAPI_RESET) { int timeout = 1000000; do { DELAY(10); request->status = ATA_IDX_INB(ch, ATA_STATUS); } while (request->status & ATA_S_BUSY && timeout--); if (request->status & ATA_S_ERROR) request->error = ATA_IDX_INB(ch, ATA_ERROR); break; } /* if write command output the data */ if (write) { if (ata_wait(request->device, (ATA_S_READY | ATA_S_DSC | ATA_S_DRQ)) < 0) { ata_prtdev(request->device,"timeout waiting for write DRQ"); request->result = EIO; break; } ata_pio_write(request, request->transfersize); } } return ATA_OP_CONTINUES; /* ATA DMA data transfer commands */ case ATA_R_DMA: /* check sanity, setup SG list and DMA engine */ if (ch->dma->load(request->device, request->data, request->bytecount, request->flags & ATA_R_READ)) { ata_prtdev(request->device, "setting up DMA failed\n"); request->result = EIO; break; } /* issue command */ if (ch->hw.command(request->device, request->u.ata.command, request->u.ata.lba, request->u.ata.count, request->u.ata.feature)) { ata_prtdev(request->device, "error issueing %s command\n", ata_cmd2str(request)); request->result = EIO; break; } /* start DMA engine */ if (ch->dma->start(ch)) { ata_prtdev(request->device, "error starting DMA\n"); request->result = EIO; break; } return ATA_OP_CONTINUES; /* ATAPI PIO commands */ case ATA_R_ATAPI: /* is this just a POLL DSC command ? */ if (request->u.atapi.ccb[0] == ATAPI_POLL_DSC) { ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | request->device->unit); DELAY(10); if (!(ATA_IDX_INB(ch, ATA_ALTSTAT)&ATA_S_DSC)) request->result = EBUSY; break; } /* start ATAPI operation */ if (ch->hw.command(request->device, ATA_PACKET_CMD, request->transfersize << 8, 0, 0)) { ata_prtdev(request->device, "error issuing ATA PACKET command\n"); request->result = EIO; break; } /* command interrupt device ? just return and wait for interrupt */ if ((request->device->param->config & ATA_DRQ_MASK) == ATA_DRQ_INTR) return ATA_OP_CONTINUES; /* wait for ready to write ATAPI command block */ { int timeout = 5000; /* might be less for fast devices */ while (timeout--) { int reason = ATA_IDX_INB(ch, ATA_IREASON); int status = ATA_IDX_INB(ch, ATA_STATUS); if (((reason & (ATA_I_CMD | ATA_I_IN)) | (status & (ATA_S_DRQ | ATA_S_BUSY))) == ATAPI_P_CMDOUT) break; DELAY(20); } if (timeout <= 0) { ata_prtdev(request->device, "timeout waiting for ATAPI ready\n"); request->result = EIO; break; } } /* this seems to be needed for some (slow) devices */ DELAY(10); /* output actual command block */ ATA_IDX_OUTSW_STRM(ch, ATA_DATA, (int16_t *)request->u.atapi.ccb, (request->device->param->config & ATA_PROTO_MASK) == ATA_PROTO_ATAPI_12 ? 6 : 8); return ATA_OP_CONTINUES; case ATA_R_ATAPI|ATA_R_DMA: /* is this just a POLL DSC command ? */ if (request->u.atapi.ccb[0] == ATAPI_POLL_DSC) { ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | request->device->unit); DELAY(10); if (!(ATA_IDX_INB(ch, ATA_ALTSTAT)&ATA_S_DSC)) request->result = EBUSY; break; } /* check sanity, setup SG list and DMA engine */ if (ch->dma->load(request->device, request->data, request->bytecount, request->flags & ATA_R_READ)) { ata_prtdev(request->device, "setting up DMA failed\n"); request->result = EIO; break; } /* start ATAPI operation */ if (ch->hw.command(request->device, ATA_PACKET_CMD, 0, 0, ATA_F_DMA)) { ata_prtdev(request->device, "error issuing ATAPI packet command\n"); request->result = EIO; break; } /* wait for ready to write ATAPI command block */ { int timeout = 5000; /* might be less for fast devices */ while (timeout--) { int reason = ATA_IDX_INB(ch, ATA_IREASON); int status = ATA_IDX_INB(ch, ATA_STATUS); if (((reason & (ATA_I_CMD | ATA_I_IN)) | (status & (ATA_S_DRQ | ATA_S_BUSY))) == ATAPI_P_CMDOUT) break; DELAY(20); } if (timeout <= 0) { ata_prtdev(request->device,"timeout waiting for ATAPI ready\n"); request->result = EIO; break; } } /* this seems to be needed for some (slow) devices */ DELAY(10); /* output actual command block */ ATA_IDX_OUTSW_STRM(ch, ATA_DATA, (int16_t *)request->u.atapi.ccb, (request->device->param->config & ATA_PROTO_MASK) == ATA_PROTO_ATAPI_12 ? 6 : 8); /* start DMA engine */ if (ch->dma->start(ch)) { request->result = EIO; break; } return ATA_OP_CONTINUES; } /* request finish here */ if (ch->dma && ch->dma->flags & ATA_DMA_LOADED) ch->dma->unload(ch); return ATA_OP_FINISHED; }
static int ata_end_transaction(struct ata_request *request) { struct ata_channel *ch = request->device->channel; int length; ATA_DEBUG_RQ(request, "end transaction"); /* clear interrupt and get status */ request->status = ATA_IDX_INB(ch, ATA_STATUS); switch (request->flags & (ATA_R_ATAPI | ATA_R_DMA | ATA_R_CONTROL)) { /* ATA PIO data transfer and control commands */ default: /* XXX Doesn't handle the non-PIO case. */ if (request->flags & ATA_R_TIMEOUT) return ATA_OP_FINISHED; /* on control commands read back registers to the request struct */ if (request->flags & ATA_R_CONTROL) { request->u.ata.count = ATA_IDX_INB(ch, ATA_COUNT); request->u.ata.lba = ATA_IDX_INB(ch, ATA_SECTOR) | (ATA_IDX_INB(ch, ATA_CYL_LSB) << 8) | (ATA_IDX_INB(ch, ATA_CYL_MSB) << 16) | ((ATA_IDX_INB(ch, ATA_DRIVE) & 0x0f) << 24); } /* if we got an error we are done with the HW */ if (request->status & ATA_S_ERROR) { request->error = ATA_IDX_INB(ch, ATA_ERROR); return ATA_OP_FINISHED; } /* are we moving data ? */ if (request->flags & (ATA_R_READ | ATA_R_WRITE)) { /* if read data get it */ if (request->flags & ATA_R_READ) ata_pio_read(request, request->transfersize); /* update how far we've gotten */ request->donecount += request->transfersize; /* do we need a scoop more ? */ if (request->bytecount > request->donecount) { /* set this transfer size according to HW capabilities */ request->transfersize = min((request->bytecount - request->donecount), request->transfersize); /* clear interrupt seen flag as we need to wait again */ request->flags &= ~ATA_R_INTR_SEEN; /* if data write command, output the data */ if (request->flags & ATA_R_WRITE) { /* if we get an error here we are done with the HW */ if (ata_wait(request->device, (ATA_S_READY | ATA_S_DSC | ATA_S_DRQ)) < 0) { ata_prtdev(request->device, "timeout waiting for write DRQ"); request->status = ATA_IDX_INB(ch, ATA_STATUS); return ATA_OP_FINISHED; } /* output data and return waiting for new interrupt */ ata_pio_write(request, request->transfersize); return ATA_OP_CONTINUES; } /* if data read command, return & wait for interrupt */ if (request->flags & ATA_R_READ) return ATA_OP_CONTINUES; } } /* done with HW */ return ATA_OP_FINISHED; /* ATA DMA data transfer commands */ case ATA_R_DMA: /* stop DMA engine and get status */ if (ch->dma->stop) request->dmastat = ch->dma->stop(ch); /* did we get error or data */ if (request->status & ATA_S_ERROR) request->error = ATA_IDX_INB(ch, ATA_ERROR); else if (request->dmastat & ATA_BMSTAT_ERROR) request->status |= ATA_S_ERROR; else request->donecount = request->bytecount; /* release SG list etc */ ch->dma->unload(ch); /* done with HW */ return ATA_OP_FINISHED; /* ATAPI PIO commands */ case ATA_R_ATAPI: length = ATA_IDX_INB(ch, ATA_CYL_LSB)|(ATA_IDX_INB(ch, ATA_CYL_MSB)<<8); switch ((ATA_IDX_INB(ch, ATA_IREASON) & (ATA_I_CMD | ATA_I_IN)) | (request->status & ATA_S_DRQ)) { case ATAPI_P_CMDOUT: /* this seems to be needed for some (slow) devices */ DELAY(10); if (!(request->status & ATA_S_DRQ)) { ata_prtdev(request->device, "command interrupt without DRQ\n"); request->status = ATA_S_ERROR; return ATA_OP_FINISHED; } ATA_IDX_OUTSW_STRM(ch, ATA_DATA, (int16_t *)request->u.atapi.ccb, (request->device->param->config & ATA_PROTO_MASK)== ATA_PROTO_ATAPI_12 ? 6 : 8); /* return wait for interrupt */ return ATA_OP_CONTINUES; case ATAPI_P_WRITE: if (request->flags & ATA_R_READ) { request->status = ATA_S_ERROR; ata_prtdev(request->device, "%s trying to write on read buffer\n", ata_cmd2str(request)); return ATA_OP_FINISHED; } ata_pio_write(request, length); request->donecount += length; /* set next transfer size according to HW capabilities */ request->transfersize = min((request->bytecount-request->donecount), request->transfersize); /* return wait for interrupt */ return ATA_OP_CONTINUES; case ATAPI_P_READ: if (request->flags & ATA_R_WRITE) { request->status = ATA_S_ERROR; ata_prtdev(request->device, "%s trying to read on write buffer\n", ata_cmd2str(request)); return ATA_OP_FINISHED; } ata_pio_read(request, length); request->donecount += length; /* set next transfer size according to HW capabilities */ request->transfersize = min((request->bytecount-request->donecount), request->transfersize); /* return wait for interrupt */ return ATA_OP_CONTINUES; case ATAPI_P_DONEDRQ: ata_prtdev(request->device, "WARNING - %s DONEDRQ non conformant device\n", ata_cmd2str(request)); if (request->flags & ATA_R_READ) { ata_pio_read(request, length); request->donecount += length; } else if (request->flags & ATA_R_WRITE) { ata_pio_write(request, length); request->donecount += length; } else request->status = ATA_S_ERROR; /* FALLTHROUGH */ case ATAPI_P_ABORT: case ATAPI_P_DONE: if (request->status & (ATA_S_ERROR | ATA_S_DWF)) request->error = ATA_IDX_INB(ch, ATA_ERROR); return ATA_OP_FINISHED; default: ata_prtdev(request->device, "unknown transfer phase\n"); request->status = ATA_S_ERROR; } /* done with HW */ return ATA_OP_FINISHED; /* ATAPI DMA commands */ case ATA_R_ATAPI|ATA_R_DMA: /* stop the engine and get engine status */ if (ch->dma->stop) request->dmastat = ch->dma->stop(ch); /* did we get error or data */ if (request->status & (ATA_S_ERROR | ATA_S_DWF)) request->error = ATA_IDX_INB(ch, ATA_ERROR); else if (request->dmastat & ATA_BMSTAT_ERROR) request->status |= ATA_S_ERROR; else request->donecount = request->bytecount; /* release SG list etc */ ch->dma->unload(ch); /* done with HW */ return ATA_OP_FINISHED; } }