static void ath79_spi_enable(struct ath79_spi *sp) { /* enable GPIO mode */ ath79_spi_wr(sp, AR71XX_SPI_REG_FS, AR71XX_SPI_FS_GPIO); /* save CTRL register */ sp->reg_ctrl = ath79_spi_rr(sp, AR71XX_SPI_REG_CTRL); sp->ioc_base = ath79_spi_rr(sp, AR71XX_SPI_REG_IOC); }
static u32 ath79_spi_txrx_mode0(struct spi_device *spi, unsigned nsecs, u32 word, u8 bits) { struct ath79_spi *sp = ath79_spidev_to_sp(spi); u32 ioc = sp->ioc_base; /* clock starts at inactive polarity */ for (word <<= (32 - bits); likely(bits); bits--) { u32 out; if (word & (1 << 31)) out = ioc | AR71XX_SPI_IOC_DO; else out = ioc & ~AR71XX_SPI_IOC_DO; /* setup MSB (to slave) on trailing edge */ ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out); ath79_spi_delay(sp, nsecs); ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out | AR71XX_SPI_IOC_CLK); ath79_spi_delay(sp, nsecs); if (bits == 1) ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out); word <<= 1; } return ath79_spi_rr(sp, AR71XX_SPI_REG_RDS); }
static int ath79_spi_setup_cs(struct spi_device *spi) { struct ath79_spi *sp = ath79_spidev_to_sp(spi); struct ath79_spi_controller_data *cdata; cdata = spi->controller_data; if (spi->chip_select && !cdata) return -EINVAL; /* enable GPIO mode */ ath79_spi_wr(sp, AR71XX_SPI_REG_FS, AR71XX_SPI_FS_GPIO); /* save CTRL register */ sp->reg_ctrl = ath79_spi_rr(sp, AR71XX_SPI_REG_CTRL); sp->ioc_base = ath79_spi_rr(sp, AR71XX_SPI_REG_IOC); /* TODO: setup speed? */ ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, 0x43); if (spi->chip_select) { int status = 0; status = gpio_request(cdata->gpio, dev_name(&spi->dev)); if (status) return status; status = gpio_direction_output(cdata->gpio, spi->mode & SPI_CS_HIGH); if (status) { gpio_free(cdata->gpio); return status; } } else { if (spi->mode & SPI_CS_HIGH) sp->ioc_base |= AR71XX_SPI_IOC_CS0; else sp->ioc_base &= ~AR71XX_SPI_IOC_CS0; ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base); } return 0; }