int i2s_codec_enable(i2s_config_type* ptri2s_config)
{
int AIn = 0, AOut = 0;
/* Codec initialization */
audiohw_preinit();
#if defined(CONFIG_I2S_TXRX)
if(ptri2s_config->bTxDMAEnable)
AOut = 1;
if(ptri2s_config->bRxDMAEnable)
AIn = 1;
audiohw_postinit(!(ptri2s_config->slave_en), AIn, AOut);
#else
#if defined(CONFIG_I2S_WM8750)
audiohw_postinit(!(ptri2s_config->slave_en), 0, 1);
#else
if(ptri2s_config->slave_en==0)
audiohw_postinit(1,1);
else
audiohw_postinit(0,1);
#endif
#endif
return 0;
}
/*
* Initialise the PP I2C and I2S.
*/
void audiohw_init(void)
{
#ifdef CPU_PP502x
/* normal outputs for CDI and I2S pin groups */
DEV_INIT2 &= ~0x300;
/*mini2?*/
DEV_INIT1 &=~0x3000000;
/*mini2?*/
/* I2S device reset */
DEV_RS |= DEV_I2S;
DEV_RS &=~DEV_I2S;
/* I2S device enable */
DEV_EN |= DEV_I2S;
/* enable external dev clock clocks */
DEV_EN |= DEV_EXTCLOCKS;
/* external dev clock to 24MHz */
outl(inl(0x70000018) & ~0xc, 0x70000018);
#else
/* device reset */
outl(inl(0xcf005030) | 0x80, 0xcf005030);
outl(inl(0xcf005030) & ~0x80, 0xcf005030);
/* device enable */
outl(inl(0xcf005000) | 0x80, 0xcf005000);
/* GPIO D06 enable for output */
outl(inl(0xcf00000c) | 0x40, 0xcf00000c);
outl(inl(0xcf00001c) & ~0x40, 0xcf00001c);
#ifdef IPOD_1G2G
/* bits 11,10 == 10 */
outl(inl(0xcf004040) & ~0x400, 0xcf004040);
outl(inl(0xcf004040) | 0x800, 0xcf004040);
#else /* IPOD_3G */
/* bits 11,10 == 01 */
outl(inl(0xcf004040) | 0x400, 0xcf004040);
outl(inl(0xcf004040) & ~0x800, 0xcf004040);
outl(inl(0xcf004048) & ~0x1, 0xcf004048);
outl(inl(0xcf000004) & ~0xf, 0xcf000004);
outl(inl(0xcf004044) & ~0xf, 0xcf004044);
/* C03 = 0 */
outl(inl(0xcf000008) | 0x8, 0xcf000008);
outl(inl(0xcf000018) | 0x8, 0xcf000018);
outl(inl(0xcf000028) & ~0x8, 0xcf000028);
#endif /* IPOD_1G2G/3G */
#endif
/* reset the I2S controller into known state */
i2s_reset();
audiohw_preinit();
}
void pcm_play_dma_init(void)
{
bitset32(&CGU_PERI, CGU_I2SOUT_APB_CLOCK_ENABLE);
I2SOUT_CONTROL = (1<<6) | (1<<3); /* enable dma, stereo */
audiohw_preinit();
pcm_dma_apply_settings();
}
void pcm_play_dma_init(void)
{
PWRCON(0) &= ~(1 << 4);
PWRCON(1) &= ~(1 << 7);
I2S40 = 0x110;
I2STXCON = 0xb100059;
I2SCLKCON = 1;
VIC0INTENABLE = 1 << IRQ_DMAC0;
audiohw_preinit();
}
int i2s_ioctl (struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg)
#endif
{
int i ;
unsigned long flags, data;
i2s_config_type* ptri2s_config;
ptri2s_config = filp->private_data;
switch (cmd) {
case I2S_SRATE:
spin_lock_irqsave(&ptri2s_config->lock, flags);
{
data = *(unsigned long*)(RALINK_SYSCTL_BASE+0x834);
data |=(1<<17);
*(unsigned long*)(RALINK_SYSCTL_BASE+0x834) = data;
data = *(unsigned long*)(RALINK_SYSCTL_BASE+0x834);
data &=~(1<<17);
*(unsigned long*)(RALINK_SYSCTL_BASE+0x834) = data;
audiohw_preinit();
}
if((arg>MAX_SRATE_HZ)||(arg<MIN_SRATE_HZ))
{
MSG("audio sampling rate %u should be %d ~ %d Hz\n", (u32)arg, MIN_SRATE_HZ, MAX_SRATE_HZ);
break;
}
ptri2s_config->srate = arg;
MSG("set audio sampling rate to %d Hz\n", ptri2s_config->srate);
spin_unlock_irqrestore(&ptri2s_config->lock, flags);
break;
case I2S_TX_VOL:
spin_lock_irqsave(&ptri2s_config->lock, flags);
if((int)arg > 127)
{
ptri2s_config->txvol = 127;
}
else if((int)arg < 96)
{
ptri2s_config->txvol = 96;
}
else
ptri2s_config->txvol = arg;
spin_unlock_irqrestore(&ptri2s_config->lock, flags);
break;
case I2S_RX_VOL:
spin_lock_irqsave(&ptri2s_config->lock, flags);
if((int)arg > 63)
{
ptri2s_config->rxvol = 63;
}
else if((int)arg < 0)
{
ptri2s_config->rxvol = 0;
}
else
ptri2s_config->rxvol = arg;
spin_unlock_irqrestore(&ptri2s_config->lock, flags);
break;
case I2S_TX_ENABLE:
spin_lock_irqsave(&ptri2s_config->lock, flags);
MSG("I2S_TXENABLE\n");
/* allocate tx buffer */
ptri2s_config->pPage0TxBuf8ptr = (u8*)pci_alloc_consistent(NULL, I2S_PAGE_SIZE*2 , &i2s_txdma_addr);
if(ptri2s_config->pPage0TxBuf8ptr==NULL)
{
MSG("Allocate Tx Page Buffer Failed\n");
return -1;
}
ptri2s_config->pPage1TxBuf8ptr = ptri2s_config->pPage0TxBuf8ptr + I2S_PAGE_SIZE;
for( i = 0 ; i < MAX_I2S_PAGE ; i ++ )
{
#if defined(CONFIG_I2S_MMAP)
ptri2s_config->pMMAPTxBufPtr[i] = ptri2s_config->pMMAPBufPtr[i];
#else
if(ptri2s_config->pMMAPTxBufPtr[i]==NULL)
ptri2s_config->pMMAPTxBufPtr[i] = kmalloc(I2S_PAGE_SIZE, GFP_KERNEL);
#endif
}
#if defined(I2S_FIFO_MODE)
#else
GdmaI2sTx((u32)ptri2s_config->pPage0TxBuf8ptr, I2S_FIFO_WREG, 0, I2S_PAGE_SIZE, i2s_dma_tx_handler, i2s_unmask_handler);
GdmaI2sTx((u32)ptri2s_config->pPage1TxBuf8ptr, I2S_FIFO_WREG, 1, I2S_PAGE_SIZE, i2s_dma_tx_handler, i2s_unmask_handler);
#endif
i2s_reset_tx_config(ptri2s_config);
ptri2s_config->bTxDMAEnable = 1;
i2s_tx_config(ptri2s_config);
if(ptri2s_config->bRxDMAEnable==0)
i2s_clock_enable(ptri2s_config);
audiohw_set_lineout_vol(1, ptri2s_config->txvol, ptri2s_config->txvol);
i2s_tx_enable(ptri2s_config);
#if defined(I2S_FIFO_MODE)
#else
GdmaUnMaskChannel(GDMA_I2S_TX0);
#endif
data = i2s_inw(RALINK_REG_INTENA);
data |=0x0400;
i2s_outw(RALINK_REG_INTENA, data);
MSG("I2S_TXENABLE done\n");
spin_unlock_irqrestore(&ptri2s_config->lock, flags);
break;
case I2S_TX_DISABLE:
spin_lock_irqsave(&ptri2s_config->lock, flags);
MSG("I2S_TXDISABLE\n");
i2s_tx_disable(ptri2s_config);
i2s_reset_tx_config(ptri2s_config);
if(ptri2s_config->bRxDMAEnable==0)
i2s_clock_disable(ptri2s_config);
//i2s_tx_disable(ptri2s_config);
if(ptri2s_config->bRxDMAEnable==0)
{
data = i2s_inw(RALINK_REG_INTENA);
data &= 0xFFFFFBFF;
i2s_outw(RALINK_REG_INTENA, data);
}
for( i = 0 ; i < MAX_I2S_PAGE ; i ++ )
{
if(ptri2s_config->pMMAPTxBufPtr[i] != NULL)
{
#if defined(CONFIG_I2S_MMAP)
dma_unmap_single(NULL, i2s_mmap_addr[i], I2S_PAGE_SIZE, DMA_TO_DEVICE);
#endif
kfree(ptri2s_config->pMMAPTxBufPtr[i]);
ptri2s_config->pMMAPTxBufPtr[i] = NULL;
}
}
pci_free_consistent(NULL, I2S_PAGE_SIZE*2, ptri2s_config->pPage0TxBuf8ptr, i2s_txdma_addr);
ptri2s_config->pPage0TxBuf8ptr = NULL;
spin_unlock_irqrestore(&ptri2s_config->lock, flags);
break;
case I2S_RX_ENABLE:
spin_lock_irqsave(&ptri2s_config->lock, flags);
MSG("I2S_RXENABLE\n");
/* allocate rx buffer */
ptri2s_config->pPage0RxBuf8ptr = (u8*)pci_alloc_consistent(NULL, I2S_PAGE_SIZE*2 , &i2s_rxdma_addr);
if(ptri2s_config->pPage0RxBuf8ptr==NULL)
{
MSG("Allocate Rx Page Buffer Failed\n");
return -1;
}
ptri2s_config->pPage1RxBuf8ptr = ptri2s_config->pPage0RxBuf8ptr + I2S_PAGE_SIZE;
for( i = 0 ; i < MAX_I2S_PAGE ; i ++ )
{
if(ptri2s_config->pMMAPRxBufPtr[i]==NULL)
ptri2s_config->pMMAPRxBufPtr[i] = kmalloc(I2S_PAGE_SIZE, GFP_KERNEL);
}
#if defined(I2S_FIFO_MODE)
#else
GdmaI2sRx(I2S_RX_FIFO_RREG, (u32)ptri2s_config->pPage0RxBuf8ptr, 0, I2S_PAGE_SIZE, i2s_dma_rx_handler, i2s_unmask_handler);
GdmaI2sRx(I2S_RX_FIFO_RREG, (u32)ptri2s_config->pPage1RxBuf8ptr, 1, I2S_PAGE_SIZE, i2s_dma_rx_handler, i2s_unmask_handler);
#endif
i2s_reset_rx_config(ptri2s_config);
ptri2s_config->bRxDMAEnable = 1;
i2s_rx_config(ptri2s_config);
#if defined(I2S_FIFO_MODE)
#else
GdmaUnMaskChannel(GDMA_I2S_RX0);
#endif
if(ptri2s_config->bTxDMAEnable==0)
i2s_clock_enable(ptri2s_config);
#if defined(CONFIG_I2S_TXRX)
audiohw_set_linein_vol(ptri2s_config->rxvol, ptri2s_config->rxvol);
#endif
i2s_rx_enable(ptri2s_config);
data = i2s_inw(RALINK_REG_INTENA);
data |=0x0400;
i2s_outw(RALINK_REG_INTENA, data);
spin_unlock_irqrestore(&ptri2s_config->lock, flags);
break;
case I2S_RX_DISABLE:
spin_lock_irqsave(&ptri2s_config->lock, flags);
MSG("I2S_RXDISABLE\n");
i2s_reset_rx_config(ptri2s_config);
if(ptri2s_config->bTxDMAEnable==0)
i2s_clock_disable(ptri2s_config);
i2s_rx_disable(ptri2s_config);
if(ptri2s_config->bRxDMAEnable==0)
{
data = i2s_inw(RALINK_REG_INTENA);
data &= 0xFFFFFBFF;
i2s_outw(RALINK_REG_INTENA, data);
}
for( i = 0 ; i < MAX_I2S_PAGE ; i ++ )
{
if(ptri2s_config->pMMAPRxBufPtr[i] != NULL)
kfree(ptri2s_config->pMMAPRxBufPtr[i]);
ptri2s_config->pMMAPRxBufPtr[i] = NULL;
}
pci_free_consistent(NULL, I2S_PAGE_SIZE*2, ptri2s_config->pPage0RxBuf8ptr, i2s_rxdma_addr);
ptri2s_config->pPage0RxBuf8ptr = NULL;
spin_unlock_irqrestore(&ptri2s_config->lock, flags);
break;
case I2S_PUT_AUDIO:
//MSG("I2S_PUT_AUDIO\n");
#if defined(I2S_FIFO_MODE)
{
long* pData ;
//MSG("I2S_PUT_AUDIO FIFO\n");
copy_from_user(ptri2s_config->pMMAPTxBufPtr[0], (char*)arg, I2S_PAGE_SIZE);
pData = ptri2s_config->pMMAPTxBufPtr[0];
for(i = 0 ; i < I2S_PAGE_SIZE>>2 ; i++ )
{
int j;
unsigned long status = i2s_inw(I2S_FF_STATUS);
while((status&0x0F)==0)
{
for(j = 0 ; j < 50 ; j++);
status = i2s_inw(I2S_FF_STATUS);
}
*((volatile uint32_t *)(I2S_TX_FIFO_WREG)) = cpu_to_le32(*pData);
if(i==16)
MSG("I2S_PUT_AUDIO FIFO[0x%08X]\n", *pData);
pData++;
}
}
break;
#else
do{
spin_lock_irqsave(&ptri2s_config->lock, flags);
if(((ptri2s_config->tx_w_idx+4)%MAX_I2S_PAGE)!=ptri2s_config->tx_r_idx)
{
ptri2s_config->tx_w_idx = (ptri2s_config->tx_w_idx+1)%MAX_I2S_PAGE;
//printk("put TB[%d] for user write\n",ptri2s_config->tx_w_idx);
#if defined(CONFIG_I2S_MMAP)
put_user(ptri2s_config->tx_w_idx, (int*)arg);
#else
copy_from_user(ptri2s_config->pMMAPTxBufPtr[ptri2s_config->tx_w_idx], (char*)arg, I2S_PAGE_SIZE);
#endif
pi2s_status->txbuffer_len++;
spin_unlock_irqrestore(&ptri2s_config->lock, flags);
break;
}
else
{
/* Buffer Full */
//printk("TBF tr=%d, tw=%d\n", ptri2s_config->tx_r_idx, ptri2s_config->tx_w_idx);
pi2s_status->txbuffer_ovrun++;
spin_unlock_irqrestore(&ptri2s_config->lock, flags);
interruptible_sleep_on(&(ptri2s_config->i2s_tx_qh));
}
}while(1);
break;
#endif
case I2S_GET_AUDIO:
#if defined(I2S_FIFO_MODE)
{
long* pData ;
pData = ptri2s_config->pMMAPRxBufPtr[0];
for(i = 0 ; i < I2S_PAGE_SIZE>>2 ; i++ )
{
int j;
unsigned long status = i2s_inw(I2S_FF_STATUS);
while((status&0x0F0)==0)
{
for(j = 0 ; j < 50 ; j++);
status = i2s_inw(I2S_FF_STATUS);
}
*pData = i2s_inw(I2S_RX_FIFO_RREG);
if(i==16)
MSG("I2S_GET_AUDIO FIFO[0x%08X]\n", *pData);
pData++;
}
copy_to_user((char*)arg, ptri2s_config->pMMAPRxBufPtr[0], I2S_PAGE_SIZE);
}
break;
#else
do{
spin_lock_irqsave(&ptri2s_config->lock, flags);
if(ptri2s_config->rx_r_idx!=ptri2s_config->rx_w_idx)
{
copy_to_user((char*)arg, ptri2s_config->pMMAPRxBufPtr[ptri2s_config->rx_r_idx], I2S_PAGE_SIZE);
ptri2s_config->rx_r_idx = (ptri2s_config->rx_r_idx+1)%MAX_I2S_PAGE;
pi2s_status->rxbuffer_len--;
spin_unlock_irqrestore(&ptri2s_config->lock, flags);
break;
}
else
{
/* Buffer Full */
//printk("RBF rr=%d, rw=%d\n", ptri2s_config->rx_r_idx, ptri2s_config->rx_w_idx);
pi2s_status->rxbuffer_ovrun++;
spin_unlock_irqrestore(&ptri2s_config->lock, flags);
interruptible_sleep_on(&(ptri2s_config->i2s_rx_qh));
}
}while(1);
break;
#endif
case I2S_DEBUG_CLKGEN:
case I2S_DEBUG_INLBK:
case I2S_DEBUG_EXLBK:
case I2S_DEBUG_CODECBYPASS:
case I2S_DEBUG_FMT:
case I2S_DEBUG_RESET:
i2s_debug_cmd(cmd, arg);
break;
default :
MSG("i2s_ioctl: command format error\n");
}
return 0;
}
static int i2s_dev_open(i2s_config_type* ptri2s_config)
{
int i, result, db, srate;
unsigned int data = 0;
MSG("i2s_dev_open \n");
/* set i2s clk */
data = i2s_inw(RALINK_SYSCTL_BASE+0x30);
data &= 0xFFFF00FF;
#ifdef I2S_MS_MODE
#ifdef I2S_IN_CLKSRC
data |= 0x00008000;
/* for internal clock = 15.625 Mhz */
switch(ptri2s_config->srate)
{
case 8000:
srate = 60<<8;
break;
case 11250:
srate = 43<<8;
break;
case 16000:
srate = 30<<8;
break;
case 22050:
srate = 21<<8;
break;
case 24000:
srate = 19<<8;
break;
case 32000:
srate = 14<<8;
break;
case 44100:
srate = 10<<8;
break;
case 48000:
srate = 9<<8;
break;
case 88200:
srate = 7<<8;
break;
case 96000:
srate = 4<<8;
break;
default:
srate = 10<<8;
}
#ifdef FPGA_BOARD_RT3052
/* for internal clock = 12.5Mhz */
switch(ptri2s_config->srate)
{
case 8000:
srate = 48<<8;
break;
case 11250:
srate = 34<<8;
break;
case 16000:
srate = 23<<8;
break;
case 22050:
srate = 17<<8;
break;
case 24000:
srate = 15<<8;
break;
case 32000:
srate = 11<<8;
break;
case 44100:
srate = 8<<8;
break;
case 48000:
srate = 7<<8;
break;
case 88200:
srate = 5<<8;
break;
case 96000:
srate = 3<<8;
break;
default:
srate = 8<<8;
}
#endif
#else
data |= 0x0000C000;
/* for external clock = 12.288Mhz */
switch(ptri2s_config->srate)
{
case 8000:
srate = 48<<8;
break;
case 11250:
srate = 34<<8;
break;
case 16000:
srate = 23<<8;
break;
case 22050:
srate = 17<<8;
break;
case 24000:
srate = 15<<8;
break;
case 32000:
srate = 11<<8;
break;
case 44100:
srate = 8<<8;
break;
case 48000:
srate = 7<<8;
break;
case 88200:
srate = 5<<8;
break;
case 96000:
srate = 3<<8;
break;
default:
srate = 8<<8;
}
#endif
data |= srate;
#else
/* for external clock = 12.288Mhz, I2S slave mode */
switch(ptri2s_config->srate)
{
case 8000:
srate = 0x04;
break;
case 11250:
srate = 0x10;
break;
case 16000:
srate = 0x14;
break;
case 22050:
srate = 0x38;
break;
case 24000:
srate = 0x38;
break;
case 32000:
srate = 0x18;
break;
case 44100:
srate = 0x20;
break;
case 48000:
srate = 0x00;
break;
case 88200:
srate = 0x00;
break;
case 96000:
srate = 0x1C;
break;
default:
srate = 0x20;
}
#endif
i2s_outw(RALINK_SYSCTL_BASE+0x30, data);
MSG("RALINK_SYSCTL_BASE+0x30=0x%08X\n",data);
/* set share pins to i2c */
data = i2s_inw(RALINK_REG_GPIOMODE);
data &= 0xFFFFFFE0;
data |= 0x00000008;
i2s_outw(RALINK_REG_GPIOMODE, data);
MSG("RALINK_REG_GPIOMODE=0x%08X\n",data);
/* DAC initialization */
audiohw_preinit();
audiohw_postinit();
#ifdef I2S_MS_MODE
#else
audiohw_set_frequency(srate);
#endif
//saudiohw_enable_output();
//db = tenthdb2master(ptri2s_config->vol);
//audiohw_set_lineout_vol(db, db);
/* set I2S_I2SCFG */
data = i2s_inw(I2S_I2SCFG);
data &= 0xFFFFFF80;
data |= REGBIT(ptri2s_config->ff_thres, I2S_FF_THRES);
data |= REGBIT(ptri2s_config->ch_swap, I2S_CH_SWAP);
#ifdef I2S_MS_MODE
data &= ~REGBIT(0x1, I2S_SLAVE_EN);
data &= ~REGBIT(0x1, I2S_CLK_OUT_DIS);
#else
data |= REGBIT(0x1, I2S_SLAVE_EN);
data |= REGBIT(0x1, I2S_CLK_OUT_DIS);
#endif
i2s_outw(I2S_I2SCFG, data);
MSG("I2S_I2SCFG=%X\n",data);
i2s_dev_enable(ptri2s_config);
return I2S_OK;
}