void govw_reg_dump(void)
{
auto_pll_divisor(DEV_GOVW,CLK_ENABLE,0,0);
DPRINT("========== GOVW register dump ==========\n");
vpp_reg_dump(REG_GOVW_BEGIN,REG_GOVW_END-REG_GOVW_BEGIN);
DPRINT("GOVW enable %d\n",vppif_reg32_read(GOVW_HD_MIF_ENABLE));
DPRINT("color mode %s\n",vpp_colfmt_str[govw_get_color_format()]);
DPRINT("Y addr 0x%x,C addr 0x%x\n",vppif_reg32_in(REG_GOVW_HD_YSA),vppif_reg32_in(REG_GOVW_HD_CSA));
DPRINT("Y width %d,fb width %d\n",vppif_reg32_read(GOVW_HD_YPXLWID),vppif_reg32_read(GOVW_HD_YBUFWID));
DPRINT("C width %d,fb width %d\n",vppif_reg32_read(GOVW_HD_CPXLWID),vppif_reg32_read(GOVW_HD_CBUFWID));
DPRINT("---------- GOVW TG ----------\n");
DPRINT("TG enable %d, wait ready enable %d\n",vppif_reg32_read(GOVW_TG_ENABLE),vppif_reg32_read(GOVW_TG_WATCHDOG_ENABLE));
DPRINT("clk %d,Read cyc %d\n",vpp_get_base_clock(VPP_MOD_GOVW),vppif_reg32_read(GOVW_TG_RDCYC));
DPRINT("H total %d, beg %d, end %d\n",vppif_reg32_read(GOVW_TG_H_ALLPIXEL),
vppif_reg32_read(GOVW_TG_H_ACTBG),vppif_reg32_read(GOVW_TG_H_ACTEND));
DPRINT("V total %d, beg %d, end %d\n",vppif_reg32_read(GOVW_TG_V_ALLLINE),
vppif_reg32_read(GOVW_TG_V_ACTBG),vppif_reg32_read(GOVW_TG_V_ACTEND));
DPRINT("VBIE %d,PVBI %d\n",vppif_reg32_read(GOVW_TG_VBIE),vppif_reg32_read(GOVW_TG_PVBI));
DPRINT("Watch dog 0x%x\n",vppif_reg32_read(GOVW_TG_WATCHDOG_VALUE));
DPRINT("INT MIF C err %d,Y err %d,TG err %d\n",vppif_reg32_read(GOVW_INT_MIFCERR_ENABLE),
vppif_reg32_read(GOVW_INT_MIFYERR_ENABLE),vppif_reg32_read(GOVW_INT_TGERR_ENABLE));
auto_pll_divisor(DEV_GOVW,CLK_DISABLE,0,0);
}
void scl_reg_dump(void)
{
auto_pll_divisor(DEV_SCL444U,CLK_ENABLE,0,0);
DPRINT("========== SCL register dump ==========\n");
vpp_reg_dump(REG_SCL_BASE1_BEGIN,REG_SCL_BASE1_END-REG_SCL_BASE1_BEGIN);
vpp_reg_dump(REG_SCL_BASE2_BEGIN,REG_SCL_BASE2_END-REG_SCL_BASE2_BEGIN);
DPRINT("---------- SCL scale ----------\n");
DPRINT("scale enable %d\n",vppif_reg32_read(SCL_ALU_ENABLE));
DPRINT("scale width H %d,V %d\n",vppif_reg32_read(SCL_HXWIDTH),vppif_reg32_read(SCL_VXWIDTH));
DPRINT("H scale up %d,V scale up %d\n",vppif_reg32_read(SCL_HSCLUP_ENABLE),vppif_reg32_read(SCL_VSCLUP_ENABLE));
DPRINT("H sub step %d,thr %d,step %d,sub step cnt %d,i step cnt %d\n",vppif_reg32_read(SCL_H_SUBSTEP),
vppif_reg32_read(SCL_H_THR),vppif_reg32_read(SCL_H_STEP),vppif_reg32_read(SCL_H_I_SUBSTEPCNT),vppif_reg32_read(SCL_H_I_STEPCNT));
DPRINT("V sub step %d,thr %d,step %d,sub step cnt %d,i step cnt %d\n",vppif_reg32_read(SCL_V_SUBSTEP),
vppif_reg32_read(SCL_V_THR),vppif_reg32_read(SCL_V_STEP),vppif_reg32_read(SCL_V_I_SUBSTEPCNT),vppif_reg32_read(SCL_V_I_STEPCNT));
DPRINT("---------- SCL filter ----------\n");
DPRINT("DEBLOCK %d,boundary 1st 0x%x,2nd 0x%x\n,",vppif_reg32_read(SCL_DEBLOCK_ENABLE),
vppif_reg32_read(SCL_1ST_LAYER_BOUNDARY),vppif_reg32_read(SCL_2ND_LAYER_BOUNDARY));
DPRINT("FIELD DEFLICKER %d,up %s down,thr Y %d,C %d\n",vppif_reg32_read(SCL_FIELD_DEFLICKER),vppif_reg32_read(SCL_FIELD_DEFLICKER)?"&":"or",
vppif_reg32_read(SCL_FIELD_FILTER_Y_THD),vppif_reg32_read(SCL_FIELD_FILTER_C_THD));
DPRINT("FRAME DEFLICKER %d,%s,2^%d,scene chg %d\n",vppif_reg32_read(SCL_FRAME_DEFLICKER),vppif_reg32_read(SCL_FRAME_FILTER_RGB)?"RGB":"Y",
vppif_reg32_read(SCL_FRAME_FILTER_SAMPLER),vppif_reg32_read(SCL_FR_FILTER_SCENE_CHG_THD));
DPRINT("CSC enable %d,CSC clamp %d\n",vppif_reg32_read(SCL_CSC_ENABLE),vppif_reg32_read(SCL_CSC_CLAMP_ENABLE));
DPRINT("---------- SCL TG ----------\n");
DPRINT("TG source : %s\n",(vppif_reg32_read(SCL_TG_GOVWTG_ENABLE))?"GOVW":"SCL");
DPRINT("TG enable %d, wait ready enable %d\n",vppif_reg32_read(SCL_TG_ENABLE),vppif_reg32_read(SCL_TG_WATCHDOG_ENABLE));
DPRINT("clk %d,Read cyc %d,1T %d\n",vpp_get_base_clock(VPP_MOD_SCL),vppif_reg32_read(SCL_TG_RDCYC),vppif_reg32_read(SCL_READCYC_1T));
DPRINT("H total %d, beg %d, end %d\n",vppif_reg32_read(SCL_TG_H_ALLPIXEL),vppif_reg32_read(SCL_TG_H_ACTBG),vppif_reg32_read(SCL_TG_H_ACTEND));
DPRINT("V total %d, beg %d, end %d\n",vppif_reg32_read(SCL_TG_V_ALLLINE),vppif_reg32_read(SCL_TG_V_ACTBG),vppif_reg32_read(SCL_TG_V_ACTEND));
DPRINT("VBIE %d,PVBI %d\n",vppif_reg32_read(SCL_TG_VBIE),vppif_reg32_read(SCL_TG_PVBI));
DPRINT("Watch dog 0x%x\n",vppif_reg32_read(SCL_TG_WATCHDOG_VALUE));
DPRINT("---------- SCLR FB ----------\n");
DPRINT("SCLR MIF enable %d,MIF2 enable %d\n",vppif_reg32_read(SCLR_MIF_ENABLE),vppif_reg32_read(SCLR_MIF2_ENABLE));
DPRINT("color format %s\n",vpp_colfmt_str[sclr_get_color_format()]);
DPRINT("color bar enable %d,mode %d,inv %d\n",vppif_reg32_read(SCLR_COLBAR_ENABLE),vppif_reg32_read(SCLR_COLBAR_MODE),vppif_reg32_read(SCLR_COLBAR_INVERSION));
DPRINT("sourc mode : %s,H264 %d\n",(vppif_reg32_read(SCLR_TAR_DISP_FMT))?"field":"frame",vppif_reg32_read(SCLR_MEDIAFMT_H264));
DPRINT("Y addr 0x%x, C addr 0x%x\n",vppif_reg32_in(REG_SCLR_YSA),vppif_reg32_in(REG_SCLR_CSA));
#ifdef REG_SCLR_YSA2
DPRINT("Y addr2 0x%x, C addr2 0x%x\n",vppif_reg32_in(REG_SCLR_YSA2),vppif_reg32_in(REG_SCLR_CSA2));
#endif
DPRINT("width %d, fb width %d\n",vppif_reg32_read(SCLR_YPXLWID),vppif_reg32_read(SCLR_YBUFWID));
DPRINT("H crop %d, V crop %d\n",vppif_reg32_read(SCLR_HCROP),vppif_reg32_read(SCLR_VCROP));
DPRINT("---------- SCLW FB ----------\n");
DPRINT("SCLW MIF enable %d\n",vppif_reg32_read(SCLW_MIF_ENABLE));
DPRINT("color format %s\n",vpp_colfmt_str[sclw_get_color_format()]);
DPRINT("Y addr 0x%x, C addr 0x%x\n",vppif_reg32_in(REG_SCLW_YSA),vppif_reg32_in(REG_SCLW_CSA));
DPRINT("Y width %d, fb width %d\n",vppif_reg32_read(SCLW_YPXLWID),vppif_reg32_read(SCLW_YBUFWID));
DPRINT("C width %d, fb width %d\n",vppif_reg32_read(SCLW_CPXLWID),vppif_reg32_read(SCLW_CBUFWID));
DPRINT("Y err %d, C err %d\n",vppif_reg32_read(SCLW_INTSTS_MIFYERR),vppif_reg32_read(SCLW_INTSTS_MIFCERR));
auto_pll_divisor(DEV_SCL444U,CLK_DISABLE,0,0);
}
void lcd_blt_set_pwm(int no, int level, int freq)
{
int clock = auto_pll_divisor(DEV_PWM,GET_FREQ, 0, 0);
int period, duty, scalar;
clock = clock / freq;
scalar = 0;
period = 2000;
while(period > 1023) {
scalar++;
period = clock / scalar;
}
duty = (period*level)/100;
duty = (duty)? (duty-1):0;
scalar = scalar-1;
period = period -1;
pwm_set_period(no,period);
pwm_set_duty(no,duty);
pwm_set_scalar(no,scalar);
if (g_pwm_setting.config)
pwm_set_control(no,(level)? 0x36:0x8);
else
pwm_set_control(no,(level)? 0x34:0x8);
pwm_set_gpio(no,level);
}
static void wmt_kpad_hw_init(void)
{
unsigned int status;
DPRINTK("Start\n");
/*Set ROW4 share pin to KPAD mode*/
KEYPAD_PIN_SHARING_SEL_VAL &= ~KEYPAD_PIN_SHARE;
/*Enable ROW0~3*/
KEYPAD_GPIO_CTRL_VAL &= ~KEYPAD_GPIO_MASK;
/*Enable ROW0~3 Pull-up/down & pull down*/
//KEYPAD_GPIO_PULL_CTRL_VAL &= ~KEYPAD_GPIO_MASK;
KEYPAD_GPIO_PULL_CTRL_VAL |= KEYPAD_GPIO_MASK;
KEYPAD_GPIO_PULL_EN_VAL |= KEYPAD_GPIO_MASK;
/*
* Turn on keypad clocks.
*/
auto_pll_divisor(DEV_KEYPAD, CLK_ENABLE, 0, 0);
/* Clean keypad matrix input control registers. */
kpad.regs->kpmcr = 0;
/*
* Simply disable keypad direct input function first.
* Also clear all direct input enable bits.
*/
kpad.regs->kpdcr = 0;
status = kpad.regs->kpdsr;
/*
* Simply clean any exist keypad matrix status.
*/
status = kpad.regs->kpstr;
kpad.regs->kpstr |= status;
if (kpad.regs->kpstr != 0)
printk(KERN_ERR "[kpad] clear status failed!\n");
//printk("[%s] 5\n",__func__);
/*
* Set keypad debounce time to be about 125 ms.
*/
kpad.regs->kpmir = KPMIR_DI(0x0FFF) | KPMIR_SI(0x01);
kpad.regs->kpdir = KPDIR_DI(0x0FFF);
/*
* Enable keypad direct input with interrupt enabled and
* automatic scan on activity.
*/
/*Active High*/
//kpad.regs->kpicr &= ~KPICR_IRIMASK;
/*Active Low*/
kpad.regs->kpicr |= KPICR_IRIMASK;
/*Ignore Multiple Key press disable*/
kpad.regs->kpdcr |= KPDCR_EN | KPDCR_IEN | KPDCR_ASA | KPDCR_DEN(DIRECT_EN) ;//|KPDCR_IMK;
DPRINTK("End\n");
}
static void kpad_close(struct input_dev *dev)
{
DPRINTK("Start\n");
if (--kpad.ref) {
DPRINTK("End1\n");
return;
}
/*
* Free interrupt resource
*/
kpad.regs->kpmcr = 0;
free_irq(kpad.irq, dev);
#ifdef USE_HOME
free_irq(IRQ_GPIO, NULL);
#endif
/*Disable clock*/
auto_pll_divisor(DEV_KEYPAD, CLK_DISABLE, 0, 0);
/*
* Unregister input device driver
*/
input_unregister_device(dev);
DPRINTK("End2\n");
}
void restore_plla_speed(unsigned int *plla_div)
{
auto_pll_divisor(DEV_ARM, SET_PLLDIV, 2, 300);
PMARM_VAL = plla_div[0];/*arm_div*/
check_pmc_busy();
PML2C_VAL = plla_div[1];/*l2c_div*/
check_pmc_busy();
PML2CTAG_VAL = plla_div[2];/*l2c_tag_div*/
check_pmc_busy();
PML2CDATA_VAL = plla_div[3];/*l2c_data_div*/
check_pmc_busy();
PML2CAXI_VAL = plla_div[4];/*l2c_axi_div*/
check_pmc_busy();
PMDBGAPB_VAL = plla_div[5];/*dbg_apb_div*/
check_pmc_busy();
PMPMA_VAL = plla_div[6];
check_pmc_busy();
PMNA12_VAL = plla_div[7];
check_pmc_busy();
PMMALI_VAL = plla_div[8];
check_pmc_busy();
PMAHB_VAL = plla_div[9];
check_pmc_busy();
PMAPB0_VAL = plla_div[10];
check_pmc_busy();
PMPMB_VAL = plla_div[11];
check_pmc_busy();
}
/*!
* \Init gpio setting
*
* \retval none
*/
static void vid_gpio_init(vid_mode mode)
{
#ifdef __KERNEL__
auto_pll_divisor(DEV_VID, CLK_ENABLE, 0, 0);
GPIO_CTRL_GP8_VDIN_BYTE_VAL = 0x0;
GPIO_PULL_EN_GP8_VDIN_BYTE_VAL = 0x0;
GPIO_CTRL_GP9_VSYNC_BYTE_VAL &= ~(BIT0|BIT1|BIT2);
GPIO_PULL_EN_GP9_VSYNC_BYTE_VAL &= ~(BIT0|BIT1|BIT2);
GPIO_PIN_SHARING_SEL_4BYTE_VAL |= BIT12;// 0 , not invert 1 , invert
GPIO_CTRL_GP31_PWM_BYTE_VAL &= ~BIT0;
GPIO_PIN_SHARING_SEL_4BYTE_VAL |= BIT11;// 1, 24MHZ output 0 , SPISS 0
#else
pGpio_Reg->CTRL_GP8_VDIN_byte = 0x0;
pGpio_Reg->PULL_EN_GP8_VDIN_byte = 0x0;
pGpio_Reg->CTRL_GP9_VSYNC_byte &= ~(BIT0|BIT1|BIT2);
pGpio_Reg->PULL_EN_GP9_VSYNC_byte &= ~ (BIT0|BIT1|BIT2);
pGpio_Reg->PIN_SHARING_SEL_4byte |= BIT31;//DVO disable
pGpio_Reg->PIN_SHARING_SEL_4byte &= ~BIT23;
#endif
return;
} /* End of vid_gpio_init()*/
void ge_clock_enable(int enable)
{
int clk_en;
/*
* if your enable clock with auto_pll_divisor() twice,
* then you have to call it at least twice to disable clock.
* It is really bad.
*/
if (enable) {
auto_pll_divisor(DEV_GE, CLK_ENABLE, 0, 0);
} else {
do {
clk_en = auto_pll_divisor(DEV_GE, CLK_DISABLE, 0, 0);
} while (clk_en);
}
}
/*-----------------------------------------------------------------------
* Initialization
*/
void i2c3_init(int speed, int slaveaddr)
{
unsigned short tmp ;
auto_pll_divisor(DEV_I2C3, CLK_ENABLE, 0, 0);
auto_pll_divisor(DEV_I2C3, SET_DIV, 2, 20);
/**/
/* software initial*/
i2c.regs = (struct I2C_REG *)BA_I2C3;
i2c.irq_no = 15;
/*set i2c master transfer mode*/
if (i2c_xfer_mode == I2C_STANDARD_MODE)
i2c.i2c_mode = I2C_STANDARD_MODE ;
else if (i2c_xfer_mode == I2C_FAST_MODE)
i2c.i2c_mode = I2C_FAST_MODE ;
else if (i2c_xfer_mode == I2C_HS_MODE)
i2c.i2c_mode = I2C_HS_MODE ;
i2c.isr_nack = 0 ;
i2c.isr_byte_end = 0 ;
i2c.isr_timeout = 0 ;
/* Set I2C/GPIO pinmux to IIC funciton*/
/* Set bit[0-3] to zero*/
GPIO_CTRL_I2C &= ~(GPIO_I2C3_SCL | GPIO_I2C3_SDA);
GPIO_PAD_EN_I2C |= (GPIO_I2C3_SCL_PULL_EN |
GPIO_I2C3_SDA_PULL_EN);
GPIO_PAD_PU_I2C |= (GPIO_I2C3_SCL_PULL_UP |
GPIO_I2C3_SDA_PULL_UP);
/* Ensure I2C clock is enabled*/
/*set i2c master register */
i2c.regs->IICCR = 0;
i2c.regs->IICDIV = 12; /* 12MHz input clk directly*/
i2c.regs->IICISR = I2C_ISR_ALL_WRITE_CLEAR;
i2c.regs->IICIMR = I2C_IMR_ALL_ENABLE;
i2c.regs->IICCR = I2C_CR_ENABLE;
tmp = i2c.regs->IICSR; /* Read clear "received ACK bit"*/
i2c.regs->IICISR = I2C_ISR_ALL_WRITE_CLEAR;
if (i2c.i2c_mode == I2C_STANDARD_MODE)
i2c.regs->IICTR = I2C_TR_STD_VALUE ; /* 0x8064*/
else if (i2c.i2c_mode == I2C_FAST_MODE)
i2c.regs->IICTR = I2C_TR_FAST_VALUE ; /* 0x8019*/
return ;
}
static int wmt_pdm_init(void)
{
wmt_pdm.irq_no = IRQ_PCM;
// Before control pcm-module, enable pcm clock first
PMCEL_VAL |= BIT16;
// set pcm_clk_source = 62464khz
//auto_pll_divisor(DEV_PCM, CLK_ENABLE, 0, 0);
//auto_pll_divisor(DEV_PCM, SET_PLLDIV, 1, 62464);
wmt_pdm.pcm_clk_src = auto_pll_divisor(DEV_PCM, GET_FREQ, 0, 0);
wmt_pdm.pcm_clk_src /= 1000;
wmt_pdm.pdm_enable = 0;
printk("wmt_pdm_init: pcm_clk_src=%d \n\r", wmt_pdm.pcm_clk_src);
if (wmt_pdm_module_enable) {
/* disable GPIO and Pull Down mode */
/* Bit1:I2SDACDAT1=PCMSYNC, Bit2:I2SDACDAT2=PCMCLK, Bit3:I2SDACDAT3=PCMIN, Bit4:I2SADCMCLK=PCMOUT */
GPIO_CTRL_GP10_I2S_BYTE_VAL &= ~(BIT1 | BIT2 | BIT3 | BIT4);
GPIO_PULL_EN_GP10_I2S_BYTE_VAL &= ~(BIT1 | BIT2 | BIT3 | BIT4);
/* set to pcm mode */
// select PCMMCLK[bit0], PCMSYNC[bit17:16], PCMCLK[19:18], PCMIN[20], PCMOUT[22:21]
GPIO_PIN_SHARING_SEL_4BYTE_VAL &= ~(BIT0 | BIT16 | BIT18 | BIT21);
GPIO_PIN_SHARING_SEL_4BYTE_VAL |= (BIT17 | BIT19 | BIT20 | BIT22);
}
// set pcm control register
PCMCR_VAL |= (PCMCR_TXFF_RST | PCMCR_RXFF_RST);
//PCMCR_VAL |= 0x00880000; // TX/RX Fifo Threshold A
PCMCR_VAL &= ~(PCMCR_BCLK_SEL);
PCMCR_VAL &= ~PCMCR_SLAVE; // master mode
// set pcm format register
PCMDFCR_VAL = 0;
PCMDFCR_VAL |= (PCMDFCR_WR_AL | PCMDFCR_TX_AL | PCMDFCR_RX_AL | PCMDFCR_RD_AL);
PCMDFCR_VAL |= (PCMDFCR_TX_SZ_14 | PCMDFCR_RX_SZ_14);
//PCMDFCR_VAL |= (PCMDFCR_TX_SZ_08 | PCMDFCR_RX_SZ_08);
//
// request irq
//
/*if (request_irq(wmt_pdm.irq_no, &wmt_pdm_irq_handler, IRQF_DISABLED, "wmt_pdm", NULL)){
printk(KERN_ERR "PCM_IRQ Request Failed!\n");
}
PCMCR_VAL |= (PCMCR_IRQ_EN | PCMCR_TXUND_EN | PCMCR_RXOVR_EN);
*/
return 0 ;
}
static void mali_enable_clock(int enable)
{
int clk_en;
/*
* if your enable clock with auto_pll_divisor() twice,
* then you have to call it at least twice to disable clock.
* It is really bad.
*/
if (enable) {
auto_pll_divisor(DEV_MALI, CLK_ENABLE, 0, 0);
#if MALI_DEBUG
printk("Mali clock enabled\n");
#endif
} else {
do {
clk_en = auto_pll_divisor(DEV_MALI, CLK_DISABLE, 0, 0);
} while (clk_en);
#if MALI_DEBUG
printk("Mali clock disabled\n");
#endif
}
}
static void dma_resume(void)
{
struct dma_regs_s *dma_regs ;
auto_pll_divisor(DEV_DMA, CLK_ENABLE, 0, 0);
dma_regs = (struct dma_regs_s *) (io_p2v(DMA_CTRL_CFG_BASE_ADDR)) ;
/*dma_regs->GCR = ( DMA_GCR_GDMA_ENABLE | DMA_GCR_PRIORITY_FIXED | DMA_GCR_GINT_ENABLE ) ;*/
dma_regs->DMA_GCR |= DMA_GLOBAL_EN;
dma_regs->DMA_ISR = ALL_INT_CLEAR;
dma_regs->DMA_IER |= ALL_INT_EN;
dma_regs->DMA_TMR &= ~SCHEDULE_RR_DISABLE; /*use RR schedule*/
dma_regs->DMA_MRPR = (unsigned int)dma_mem_phy;
/*
return 0;
*/
}
/*!
* \Init gpio setting
*
* \retval none
*/
static void vid_gpio_init(vid_mode mode)
{
auto_pll_divisor(DEV_VID, CLK_ENABLE, 0, 0);
GPIO_CTRL_GP8_VDIN_BYTE_VAL = 0x0;
GPIO_PULL_EN_GP8_VDIN_BYTE_VAL = 0x0;
GPIO_CTRL_GP9_VSYNC_BYTE_VAL &= ~(BIT0|BIT1|BIT2);
GPIO_PULL_EN_GP9_VSYNC_BYTE_VAL &= ~(BIT0|BIT1|BIT2);
GPIO_PIN_SHARING_SEL_4BYTE_VAL |= BIT12;// 0 , not invert 1 , invert
GPIO_CTRL_GP31_BYTE_VAL &= ~BIT4;//24Mhz on , not set to GPIO
return;
} /* End of vid_gpio_init()*/
/*!
* \brief
* release CMOS module
* \retval 0 if success
*/
int wmt_vid_close(vid_mode mode)
{
TRACE("Enter\n");
auto_pll_divisor(DEV_VID, CLK_DISABLE, 0, 0);
GPIO_CTRL_GP31_BYTE_VAL |= BIT4;//24Mhz off , set to GPIO
if(mode == VID_MODE_CMOS) {
VID_REG_SET32( REG_VID_CMOS_EN, 0x0); /* disable CMOS */
}
else {
int value = REG32_VAL(REG_VID_TVDEC_CTRL);
VID_REG_SET32( REG_VID_TVDEC_CTRL, (value & 0xFFFFFFE)); /* disable TV decoder */
}
TRACE("Leave\n");
return 0;
} /* End of wmt_vid_close() */
/*!
* \brief
* release CMOS module
* \retval 0 if success
*/
int wmt_vid_close(vid_mode mode)
{
TRACE("Enter\n");
auto_pll_divisor(DEV_VID, CLK_DISABLE, 0, 0);
GPIO_PIN_SHARING_SEL_4BYTE_VAL &= ~BIT11;// 1, 24MHZ output 0 , SPISS 0
GPIO_CTRL_GP31_PWM_BYTE_VAL |= BIT0;
if(mode == VID_MODE_CMOS) {
VID_REG_SET32( REG_VID_CMOS_EN, 0x0); /* disable CMOS */
}
else {
int value = REG32_VAL(REG_VID_TVDEC_CTRL);
VID_REG_SET32( REG_VID_TVDEC_CTRL, (value & 0xFFFFFFE)); /* disable TV decoder */
}
TRACE("Leave\n");
return 0;
} /* End of wmt_vid_close() */
static int wmt_kpad_suspend(struct platform_device *pdev, pm_message_t state)
{
DPRINTK("Start\n");
switch (state.event) {
case PM_EVENT_SUSPEND:
/*Disable clock*/
auto_pll_divisor(DEV_KEYPAD, CLK_DISABLE, 0, 0);
#ifdef USE_HOME
wmt_control_home_irq(0);
//disable_irq_nosync(IRQ_GPIO);
#endif
break;
case PM_EVENT_FREEZE:
case PM_EVENT_PRETHAW:
default:
break;
}
DPRINTK("End2\n");
return 0;
}
static void init_clock(void)
{
auto_pll_divisor(DEV_EBM, CLK_ENABLE, 0, 0);
auto_pll_divisor(DEV_EBM, SET_DIV, 2, 400);
return;
}
/*===========================================================================*/
static int __init
wmt_dma_init(void)
{
int ch ;
int ret = 0;
struct dma_regs_s *dma_regs ;
/*
*(volatile unsigned int *)(0xD8130254) |= BIT5;
*/
auto_pll_divisor(DEV_DMA, CLK_ENABLE, 0, 0);
dma_regs = (struct dma_regs_s *) (io_p2v(DMA_CTRL_CFG_BASE_ADDR)) ;
/**/
/* software initial*/
/**/
dma_int.request_chans = 0 ;
dma_int.regs = (struct dma_regs_s *) (io_p2v(DMA_CTRL_CFG_BASE_ADDR)) ;
for (ch = 0 ; ch < MAX_DMA_CHANNELS ; ++ch) {
dma_chan[ch].channel_no = ch ;
dma_chan[ch].regs = (struct dma_regs_s *) (io_p2v(DMA_CTRL_CFG_BASE_ADDR)) ;
dma_chan[ch].irq = ch ;
dma_chan[ch].device_no = DEVICE_RESERVED ;
dma_chan[ch].in_use = 0 ;
}
/*
dma_mem_regs = (struct dma_mem_reg_s *)dma_alloc_coherent(NULL,
sizeof(struct dma_mem_reg_s), &dma_mem_phy, GFP_KERNEL);
*/
dma_mem_regs = (struct dma_mem_reg_s *) (io_p2v((DMA_CTRL_CFG_BASE_ADDR + DMA_MEM_REG_OFFSET)));
if (!dma_mem_regs) {
printk("dma memory register allocate failed\n");
ret = -1;
return ret;
}
dma_mem_phy = DMA_CTRL_CFG_BASE_ADDR + DMA_MEM_REG_OFFSET;
DPRINTK("MEM_REGS ADDR:Virt = 0x%x , Phy = 0x%x\n", dma_mem_regs , dma_mem_phy);
if (dma_mem_phy & 0x000000FF) {/*8 DW alignment*/
printk("dma memory registers did not 8 DW alignment");
ret = -1;
return ret;
}
/**/
/* hardware initial*/
/**/
dma_regs->DMA_GCR |= DMA_SW_RST ;
dma_regs->DMA_GCR |= DMA_GLOBAL_EN;
dma_regs->DMA_ISR = ALL_INT_CLEAR;
dma_regs->DMA_IER |= ALL_INT_EN;
dma_regs->DMA_TMR &= ~SCHEDULE_RR_DISABLE; /*use RR schedule*/
dma_regs->DMA_MRPR = (unsigned int)dma_mem_phy;
DPRINTK("0x%8.8X : [0x%8.8X] DMA_GSR_REG \n", \
(unsigned int)&dma_regs->GSR , dma_regs->GSR) ;
for (ch = 0 ; ch < MAX_DMA_CHANNELS ; ++ch) {
dma_mem_regs->mem_reg_group[ch].DMA_IF0CPR_CH = 0x100;
dma_mem_regs->mem_reg_group[ch].DMA_IF1CPR_CH = 0x100;
dma_regs->DMA_CCR_CH[ch] = 0x0;
}
DPRINTK("0x%8.8X : [0x%8.8X] DMA_GCR_REG \n", \
(unsigned int)&dma_regs->DMA_GCR , dma_regs->DMA_GCR) ;
for (ch = 0; ch < MAX_DMA_CHANNELS ; ++ch)
request_irq(dma_irq_no[ch], dma_irq_handler, IRQF_DISABLED, "dma", NULL);
return ret;
}
