/* sbDevicesPorInitTable */
static void sb600_devices_por_init(void)
{
device_t dev;
u8 byte;
printk(BIOS_INFO, "sb600_devices_por_init()\n");
/* SMBus Device, BDF:0-20-0 */
printk(BIOS_INFO, "sb600_devices_por_init(): SMBus Device, BDF:0-20-0\n");
dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0);
if (dev == PCI_DEV_INVALID) {
die("SMBUS controller not found\n");
/* NOT REACHED */
}
printk(BIOS_INFO, "SMBus controller enabled, sb revision is 0x%x\n",
get_sb600_revision());
/* sbPorAtStartOfTblCfg */
/* Set A-Link bridge access address. This address is set at device 14h, function 0, register 0xf0.
* This is an I/O address. The I/O address must be on 16-byte boundary. */
pci_write_config32(dev, 0xf0, AB_INDX);
/* To enable AB/BIF DMA access, a specific register inside the BIF register space needs to be configured first. */
/*Enables the SB600 to send transactions upstream over A-Link Express interface. */
axcfg_reg(0x04, 1 << 2, 1 << 2);
axindxc_reg(0x21, 0xff, 0);
/* 2.3.5:Enabling Non-Posted Memory Write for the K8 Platform */
axindxc_reg(0x10, 1 << 9, 1 << 9);
/* END of sbPorAtStartOfTblCfg */
/* sbDevicesPorInitTables */
/* set smbus iobase */
pci_write_config32(dev, 0x10, SMBUS_IO_BASE | 1);
/* enable smbus controller interface */
byte = pci_read_config8(dev, 0xd2);
byte |= (1 << 0);
pci_write_config8(dev, 0xd2, byte);
/* set smbus 1, ASF 2.0 (Alert Standard Format), iobase */
pci_write_config16(dev, 0x58, SMBUS_IO_BASE | 0x11);
/* TODO: I don't know the usage of followed two lines. I copied them from CIM. */
pci_write_config8(dev, 0x0a, 0x1);
pci_write_config8(dev, 0x0b, 0x6);
/* KB2RstEnable */
pci_write_config8(dev, 0x40, 0xd4);
/* Enable ISA Address 0-960K decoding */
pci_write_config8(dev, 0x48, 0x0f);
/* Enable ISA Address 0xC0000-0xDFFFF decode */
pci_write_config8(dev, 0x49, 0xff);
/* Enable decode cycles to IO C50, C51, C52 GPM controls. */
byte = pci_read_config8(dev, 0x41);
byte &= 0x80;
byte |= 0x33;
pci_write_config8(dev, 0x41, byte);
/* Legacy DMA Prefetch Enhancement, CIM masked it. */
/* pci_write_config8(dev, 0x43, 0x1); */
/* Disabling Legacy USB Fast SMI# */
byte = pci_read_config8(dev, 0x62);
byte |= 0x24;
pci_write_config8(dev, 0x62, byte);
/* Features Enable */
pci_write_config32(dev, 0x64, 0x829E7DBF); /* bit10: Enables the HPET interrupt. */
/* SerialIrq Control */
pci_write_config8(dev, 0x69, 0x90);
/* Test Mode, PCIB_SReset_En Mask is set. */
pci_write_config8(dev, 0x6c, 0x20);
/* IO Address Enable, CIM set 0x78 only and masked 0x79. */
/*pci_write_config8(dev, 0x79, 0x4F); */
pci_write_config8(dev, 0x78, 0xFF);
/* This register is not used on sb600. It came from older chipset. */
/*pci_write_config8(dev, 0x95, 0xFF); */
/* Set smbus iospace enable, I don't know why write 0x04 into reg5 that is reserved */
pci_write_config16(dev, 0x4, 0x0407);
/* clear any lingering errors, so the transaction will run */
outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
/* IDE Device, BDF:0-20-1 */
printk(BIOS_INFO, "sb600_devices_por_init(): IDE Device, BDF:0-20-1\n");
dev = pci_locate_device(PCI_ID(0x1002, 0x438C), 0);
/* Disable prefetch */
byte = pci_read_config8(dev, 0x63);
byte |= 0x1;
pci_write_config8(dev, 0x63, byte);
/* LPC Device, BDF:0-20-3 */
printk(BIOS_INFO, "sb600_devices_por_init(): LPC Device, BDF:0-20-3\n");
dev = pci_locate_device(PCI_ID(0x1002, 0x438D), 0);
/* DMA enable */
pci_write_config8(dev, 0x40, 0x04);
/* LPC Sync Timeout */
pci_write_config8(dev, 0x49, 0xFF);
/* Enable Tpm12_en and Tpm_legacy. I don't know what is its usage and copied from CIM. */
pci_write_config8(dev, 0x7C, 0x05);
/* P2P Bridge, BDF:0-20-4, the configuration of the registers in this dev are copied from CIM,
* TODO: I don't know what are their mean? */
printk(BIOS_INFO, "sb600_devices_por_init(): P2P Bridge, BDF:0-20-4\n");
dev = pci_locate_device(PCI_ID(0x1002, 0x4384), 0);
/* I don't know why CIM tried to write into a read-only reg! */
/*pci_write_config8(dev, 0x0c, 0x20) */ ;
/* Arbiter enable. */
pci_write_config8(dev, 0x43, 0xff);
/* Set PCDMA request into height priority list. */
/* pci_write_config8(dev, 0x49, 0x1) */ ;
pci_write_config8(dev, 0x40, 0x26);
/* I don't know why CIM set reg0x1c as 0x11.
* System will block at sdram_initialize() if I set it before call sdram_initialize().
* If it is necessary to set reg0x1c as 0x11, please call this function after sdram_initialize().
* pci_write_config8(dev, 0x1c, 0x11);
* pci_write_config8(dev, 0x1d, 0x11);*/
/*CIM set this register; but I didn't find its description in RPR.
On DBM690T platform, I didn't find different between set and skip this register.
But on Filbert platform, the DEBUG message from serial port on Peanut board can't be displayed
after the bit0 of this register is set.
pci_write_config8(dev, 0x04, 0x21);
*/
pci_write_config8(dev, 0x0d, 0x40);
pci_write_config8(dev, 0x1b, 0x40);
/* Enable PCIB_DUAL_EN_UP will fix potential problem with PCI cards. */
pci_write_config8(dev, 0x50, 0x01);
/* SATA Device, BDF:0-18-0, Non-Raid-5 SATA controller */
printk(BIOS_INFO, "sb600_devices_por_init(): SATA Device, BDF:0-18-0\n");
dev = pci_locate_device(PCI_ID(0x1002, 0x4380), 0);
/*PHY Global Control, we are using A14.
* default: 0x2c40 for ASIC revision A12 and below
* 0x2c00 for ASIC revision A13 and above.*/
pci_write_config16(dev, 0x86, 0x2C00);
/* PHY Port0-3 Control */
pci_write_config32(dev, 0x88, 0xB400DA);
pci_write_config32(dev, 0x8c, 0xB400DA);
pci_write_config32(dev, 0x90, 0xB400DA);
pci_write_config32(dev, 0x94, 0xB400DA);
/* Port0-3 BIST Control/Status */
pci_write_config8(dev, 0xa5, 0xB8);
pci_write_config8(dev, 0xad, 0xB8);
pci_write_config8(dev, 0xb5, 0xB8);
pci_write_config8(dev, 0xbd, 0xB8);
}
/* sbDevicesPorInitTable */
static void sb800_devices_por_init(void)
{
device_t dev;
u8 byte;
printk(BIOS_INFO, "sb800_devices_por_init()\n");
/* SMBus Device, BDF:0-20-0 */
printk(BIOS_INFO, "sb800_devices_por_init(): SMBus Device, BDF:0-20-0\n");
dev = PCI_DEV(0, 0x14, 0);//pci_locate_device(PCI_ID(0x1002, 0x4385), 0);
if (dev == PCI_DEV_INVALID) {
die("SMBUS controller not found\n");
/* NOT REACHED */
}
printk(BIOS_INFO, "SMBus controller enabled, sb revision is A%x\n",
get_sb800_revision());
/* sbPorAtStartOfTblCfg */
/* rpr 4.1.Set A-Link bridge access address.
* This is an I/O address. The I/O address must be on 16-byte boundry. */
//pci_write_config32(dev, 0xf0, AB_INDX);
pmio_write(0xE0, AB_INDX & 0xFF);
pmio_write(0xE1, (AB_INDX >> 8) & 0xFF);
pmio_write(0xE2, (AB_INDX >> 16) & 0xFF);
pmio_write(0xE3, (AB_INDX >> 24) & 0xFF);
/* To enable AB/BIF DMA access, a specific register inside the BIF register space needs to be configured first. */
/* 4.2:Enables the SB800 to send transactions upstream over A-Link Express interface. */
axcfg_reg(0x04, 1 << 2, 1 << 2);
//axindxc_reg(0x21, 0xff, 0);
/* 4.15:Enabling Non-Posted Memory Write for the K8 Platform */
axindxc_reg(0x10, 1 << 9, 1 << 9);
/* END of sbPorAtStartOfTblCfg */
/* sbDevicesPorInitTables */
/* set smbus iobase */
//pci_write_config32(dev, 0x90, SMBUS_IO_BASE | 1);
/* The base address of SMBUS is set in a different way with sb700. */
byte = (SMBUS_IO_BASE & 0xFF) | 1;
pmio_write(0x2c, byte & 0xFF);
pmio_write(0x2d, SMBUS_IO_BASE >> 8);
/* AcpiMMioDecodeEn */
byte = pmio_read(0x24);
byte |= 1;
byte &= ~(1 << 1);
pmio_write(0x24, byte);
/* enable smbus controller interface */
//byte = pci_read_config8(dev, 0xd2);
//byte |= (1 << 0);
//pci_write_config8(dev, 0xd2, byte);
/* KB2RstEnable */
//pci_write_config8(dev, 0x40, 0x44);
/* Enable ISA Address 0-960K decoding */
//pci_write_config8(dev, 0x48, 0x0f);
/* Enable ISA Address 0xC0000-0xDFFFF decode */
//pci_write_config8(dev, 0x49, 0xff);
/* Enable decode cycles to IO C50, C51, C52 GPM controls. */
//byte = pci_read_config8(dev, 0x41);
//byte &= 0x80;
//byte |= 0x33;
//pci_write_config8(dev, 0x41, byte);
/* Legacy DMA Prefetch Enhancement, CIM masked it. */
/* pci_write_config8(dev, 0x43, 0x1); */
/* clear any lingering errors, so the transaction will run */
outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
/* IDE Device, BDF:0-20-1 */
printk(BIOS_INFO, "sb800_devices_por_init(): IDE Device, BDF:0-20-1\n");
dev = PCI_DEV(0, 0x14, 1);//pci_locate_device(PCI_ID(0x1002, 0x439C), 0);
/* Disable prefetch */
byte = pci_read_config8(dev, 0x63);
byte |= 0x1;
pci_write_config8(dev, 0x63, byte);
/* LPC Device, BDF:0-20-3 */
printk(BIOS_INFO, "sb800_devices_por_init(): LPC Device, BDF:0-20-3\n");
dev = PCI_DEV(0, 0x14, 3);//pci_locate_device(PCI_ID(0x1002, 0x439D), 0);
/* DMA enable */
pci_write_config8(dev, 0x40, 0x04);
/* LPC Sync Timeout */
pci_write_config8(dev, 0x49, 0xFF);
/* Set LPC ROM size, it has been done in sb800_lpc_init().
* enable LPC ROM range, 0xfff8: 512KB, 0xfff0: 1MB;
* enable LPC ROM range, 0xfff8: 512KB, 0xfff0: 1MB
* pci_write_config16(dev, 0x68, 0x000e)
* pci_write_config16(dev, 0x6c, 0xfff0);*/
/* Enable Tpm12_en and Tpm_legacy. I don't know what is its usage and copied from CIM. */
pci_write_config8(dev, 0x7C, 0x05);
/* P2P Bridge, BDF:0-20-4, the configuration of the registers in this dev are copied from CIM,
*/
printk(BIOS_INFO, "sb800_devices_por_init(): P2P Bridge, BDF:0-20-4\n");
dev = PCI_DEV(0, 0x14, 4);//pci_locate_device(PCI_ID(0x1002, 0x4384), 0);
/* Arbiter enable. */
pci_write_config8(dev, 0x43, 0xff);
/* Set PCDMA request into hight priority list. */
/* pci_write_config8(dev, 0x49, 0x1) */ ;
pci_write_config8(dev, 0x40, 0x26);
pci_write_config8(dev, 0x0d, 0x40);
pci_write_config8(dev, 0x1b, 0x40);
/* Enable PCIB_DUAL_EN_UP will fix potential problem with PCI cards. */
pci_write_config8(dev, 0x50, 0x01);
/* SATA Device, BDF:0-17-0, Non-Raid-5 SATA controller */
printk(BIOS_INFO, "sb800_devices_por_init(): SATA Device, BDF:0-18-0\n");
dev = PCI_DEV(0, 0x11, 0);//pci_locate_device(PCI_ID(0x1002, 0x4390), 0);
/*PHY Global Control*/
pci_write_config16(dev, 0x86, 0x2C00);
}
static void sm_init(device_t dev)
{
u8 byte;
u32 ioapic_base;
printk(BIOS_INFO, "sm_init().\n");
ioapic_base = 0xFEC00000;//pci_read_config32(dev, 0x74) & (0xffffffe0); /* some like mem resource, but does not have enable bit */
/* Don't rename APIC ID */
/* TODO: We should call setup_ioapic() here. But kernel hangs if cpu is K8.
* We need to check out why and change back. */
clear_ioapic(ioapic_base);
//setup_ioapic(ioapic_base, 0);
/* enable serial irq */
byte = pm_ioread(0x54);
byte |= 1 << 7; /* enable serial irq function */
byte &= ~(0xF << 2);
byte |= 4 << 2; /* set NumSerIrqBits=4 */
pm_iowrite(0x54, byte);
pm_iowrite(0x00, 0x0E);
pm_iowrite(0x0B, 0x02);
/* 2.11 IO Trap Settings */
abcfg_reg(0x10090, 1 << 16, 1 << 16);
/* 4.1 ab index */
//pci_write_config32(dev, 0xF0, AB_INDX);
pm_iowrite(0xE0, AB_INDX & 0xFF);
pm_iowrite(0xE1, (AB_INDX >> 8) & 0xFF);
pm_iowrite(0xE2, (AB_INDX >> 16) & 0xFF);
pm_iowrite(0xE3, (AB_INDX >> 24) & 0xFF);
/* Initialize the real time clock */
rtc_init(0);
byte = pm_ioread(0x8);
byte |= 1 << 2 | 1 << 4;
pm_iowrite(0x08, byte);
byte = pm_ioread(0x9);
byte |= 1 << 0;
pm_iowrite(0x09, byte);
abcfg_reg(0x10060, (BIT31), BIT31);
abcfg_reg(0x1009C, (BIT4 + BIT5), BIT4 + BIT5);
abcfg_reg(0x9C, (BIT2 + BIT3 + BIT4 + BIT5 + BIT6 + BIT7), BIT2 + BIT3 + BIT4 + BIT5 + BIT6 + BIT7);
abcfg_reg(0x90, (BIT21 + BIT22 + BIT23), BIT21 + BIT22 + BIT23);
abcfg_reg(0xF0, (BIT6 + BIT5), BIT6 + BIT5);
abcfg_reg(0x10090, (BIT9 + BIT10 + BIT11 + BIT12), BIT9 + BIT10 + BIT11 + BIT12);
abcfg_reg(0x58, (BIT10), BIT10);
abcfg_reg(0xF0, (BIT3 + BIT4), BIT3 + BIT4);
abcfg_reg(0x54, (BIT1), BIT1);
//
axindxc_reg(0x02, BIT9, BIT9);
axindxc_reg(0x10, BIT9, BIT9);
/* 4.2 Enabling Upstream DMA Access */
axcfg_reg(0x04, 1 << 2, 1 << 2);
/* 4.3 Enabling PCIB Prefetch Settings */
abcfg_reg(0x10060, 1 << 20, 1 << 20);
abcfg_reg(0x10064, 1 << 20, 1 << 20);
/* 4.4 Enabling OHCI Prefetch for Performance Enhancement, A12 */
abcfg_reg(0x80, 1 << 0, 1<< 0);
/* 4.5 B-Link Client's Credit Variable Settings for the Downstream Arbitration Equation */
/* 4.6 Enabling Additional Address Bits Checking in Downstream */
abcfg_reg(0x9c, 1 << 0, 1 << 0);
//abcfg_reg(0x9c, 3 << 0, 3 << 0); //A11
/* 4.7 Set B-Link Prefetch Mode */
abcfg_reg(0x80, 3 << 17, 3 << 17);
// RPR Enabled SMI ordering enhancement. ABCFG 0x90[21]
// RPR USB Delay A-Link Express L1 State. ABCFG 0x90[17]
abcfg_reg(0x90, 1 << 17 | 1 << 21, 1 << 17 | 1 << 21);
/* 4.8 Enabling Detection of Upstream Interrupts */
abcfg_reg(0x94, 1 << 20 | 0x7FFFF, 1 << 20 | 0x00FEE);
/* 4.9: Enabling Downstream Posted Transactions to Pass Non-Posted
* Transactions for the K8 Platform (for All Revisions) */
abcfg_reg(0x10090, 1 << 8, 1 << 8);
/* 4.10:Programming Cycle Delay for AB and BIF Clock Gating */
/* 4.11:Enabling AB Int_Arbiter Enhancement (for All Revisions) */
abcfg_reg(0x10054, 0xFFFF0000, 0x01040000);
abcfg_reg(0x54, 0xFF << 16, 4 << 16);
abcfg_reg(0x54, 1 << 24, 0 << 24);
abcfg_reg(0x54, 1 << 26, 1 << 26);
abcfg_reg(0x98, 0xFFFFFF00, 0x00004700);
/* 4.12: Enabling AB and BIF Clock Gating */
abcfg_reg(0x10054, 0x0000FFFF, 0x07FF);
/* 4.13:Enabling Requester ID for upstream traffic. */
abcfg_reg(0x98, 3 << 16, 3 << 16);
abcfg_reg(0x50, 1 << 2, 0 << 2);
/* 5.2 Enabling GPP Port A/B/C/D */
//abcfg_reg(0xC0, 0xF << 4, 0xF << 4);
/* Enable SCI as irq9. */
outb(0x10, 0xC00);
outb(0x9, 0xC01);
/* Enabled IRQ input */
outb(0x9, 0xC00);
outb(0xF7, 0xC01);
abcfg_reg(0x90, 0xFFFFFFFF, 0x00F80040);
abcfg_reg(0xA0, 0xFFFFFFFF, 0x00000000);
abcfg_reg(0xA4, 0xFFFFFFFF, 0x00000000);
abcfg_reg(0xC0, 0xFFFFFFFF, 0x0000F014);
abcfg_reg(0x98, 0xFFFFFFFF, 0X01034700);
}
/* sbDevicesPorInitTable */
void sb700_devices_por_init(void)
{
device_t dev;
u8 byte;
/* SMBus Device, BDF:0-20-0 */
dev = _pci_make_tag(0, 20, 0);
/* sbPorAtStartOfTblCfg */
/* Set A-Link bridge access address. This address is set at device 14h, function 0, register 0xf0.
* This is an I/O address. The I/O address must be on 16-byte boundry. */
printk_info("set a-link bridge access address\n");
//pci_write_config32(dev, 0xf0, AB_INDX);
pci_write_config32(dev, 0xf0, 0x00000cd8);
/* To enable AB/BIF DMA access, a specific register inside the BIF register space needs to be configured first. */
/*Enables the SB600 to send transactions upstream over A-Link Express interface. */
printk_info("To enable ab bif dam access\n");
axcfg_reg(0x04, 1 << 2, 1 << 2);
axindxc_reg(0x21, 0xff, 0);
/* 2.3.5:Enabling Non-Posted Memory Write for the K8 Platform */
printk_info("Enabling Non-Posted Memory Write for the K8 Platform\n");
axindxc_reg(0x10, 1 << 9, 1 << 9);
/* END of sbPorAtStartOfTblCfg */
/* sbDevicesPorInitTables */
/* set smbus iobase */
printk_info("set smbus iobase\n");
//pci_write_config32(dev, 0x10, SMBUS_IO_BASE | 1);
//vga lycheng
pci_write_config32(dev, 0x90, SMBUS_IO_BASE | 1);
/* enable smbus controller interface */
printk_info("enable smbus controller interface\n");
byte = pci_read_config8(dev, 0xd2);
byte |= (1 << 0);
pci_write_config8(dev, 0xd2, byte);
#if 0
/* set smbus 1, ASF 2.0 (Alert Standard Format), iobase */
printk_info("enable smbus 1, ASF 2.0\n");
pci_write_config16(dev, 0x58, SMBUS_IO_BASE | 0x11);
#endif
/* TODO: I don't know the useage of followed two lines. I copied them from CIM. */
pci_write_config8(dev, 0x0a, 0x1);
pci_write_config8(dev, 0x0b, 0x6);
/* KB2RstEnable */
printk_info("KB2RstEnable\n");
pci_write_config8(dev, 0x40, 0xd4);
/* Enable ISA Address 0-960K decoding */
printk_info("Enable ISA address decoding\n");
pci_write_config8(dev, 0x48, 0x0f);
/* Enable ISA Address 0xC0000-0xDFFFF decode */
printk_info("Enable ISA address 0xc0000-0xdffff decode\n");
pci_write_config8(dev, 0x49, 0xff);
/* Enable decode cycles to IO C50, C51, C52 GPM controls. */
printk_info("Enable decode cycles to IO controls\n");
byte = pci_read_config8(dev, 0x41);
byte &= 0x80;
byte |= 0x33;
pci_write_config8(dev, 0x41, byte);
/* Legacy DMA Prefetch Enhancement, CIM masked it. */
/* pci_write_config8(dev, 0x43, 0x1); */
/* Disabling Legacy USB Fast SMI# */
printk_info("Disabling Legacy USB Fast SMI\n");
byte = pci_read_config8(dev, 0x62);
byte |= 0x24;
pci_write_config8(dev, 0x62, byte);
/* Features Enable */
printk_info("Features Enable\n");
pci_write_config32(dev, 0x64, 0x829E7DBF); /* bit10: Enables the HPET interrupt. */
/* SerialIrq Control */
printk_info("SerialIrq Control\n");
pci_write_config8(dev, 0x69, 0x90);
/* Test Mode, PCIB_SReset_En Mask is set. */
pci_write_config8(dev, 0x6c, 0x20);
/* IO Address Enable, CIM set 0x78 only and masked 0x79. */
printk_info("IO Address Enable\n");
/*pci_write_config8(dev, 0x79, 0x4F); */
pci_write_config8(dev, 0x78, 0xFF);
//#ifndef ENABLE_SATA
#if 1
/* TODO: set ide as primary, if you want to boot from IDE, you'd better set it.Or add a configuration line.*/
printk_info("set ide as primary\n");
byte = pci_read_config8(dev, 0xAD);
byte |= 0x1<<3;
byte &= ~(0x1<<4);
pci_write_config8(dev, 0xAD, byte);
/* This register is not used on sb700. It came from older chipset. */
/*pci_write_config8(dev, 0x95, 0xFF); */
#endif
/* Set smbus iospace enable, I don't know why write 0x04 into reg5 that is reserved */
printk_info("Set smbus iospace enable\n");
pci_write_config16(dev, 0x4, 0x0407);
#if 1
/* clear any lingering errors, so the transaction will run */
printk_info("IO Address Enable\n");
//OUTB(INB(0xba000000 + SMBUS_IO_BASE + SMBHSTSTAT), 0xba000000 + SMBUS_IO_BASE + SMBHSTSTAT);
OUTB(INB(BONITO_PCIIO_BASE_VA + SMBUS_IO_BASE + SMBHSTSTAT), BONITO_PCIIO_BASE_VA + SMBUS_IO_BASE + SMBHSTSTAT);
#endif
/* IDE Device, BDF:0-20-1 */
printk_info("sb700_devices_por_init(): IDE Device, BDF:0-20-1\n");
//dev = pci_locate_device(PCI_ID(0x1002, 0x438C), 0);
dev = _pci_make_tag(0, 20, 1);
/* Disable prefetch */
printk_info("Disable prefetch\n");
byte = pci_read_config8(dev, 0x63);
byte |= 0x1;
pci_write_config8(dev, 0x63, byte);
/* LPC Device, BDF:0-20-3 */
printk_info("sb700_devices_por_init(): LPC Device, BDF:0-20-3\n");
//dev = pci_locate_device(PCI_ID(0x1002, 0x438D), 0);
dev = _pci_make_tag(0, 20, 3);
/* DMA enable */
printk_info("DMA enable\n");
pci_write_config8(dev, 0x40, 0x04);
/* IO Port Decode Enable */
printk_info("IO Port Decode Enable\n");
pci_write_config8(dev, 0x44, 0xFF);
pci_write_config8(dev, 0x45, 0xFF);
pci_write_config8(dev, 0x46, 0xC3);
pci_write_config8(dev, 0x47, 0xFF);
/* IO/Mem Port Decode Enable, I don't know why CIM disable some ports.
* Disable LPC TimeOut counter, enable SuperIO Configuration Port (2e/2f),
* Alternate SuperIO Configuration Port (4e/4f), Wide Generic IO Port (64/65).
* Enable bits for LPC ROM memory address range 1&2 for 1M ROM setting.*/
printk_info("IO/Mem Port Decode Enable\n");
byte = pci_read_config8(dev, 0x48);
byte |= (1 << 1) | (1 << 0); /* enable Super IO config port 2e-2h, 4e-4f */
byte |= (1 << 3) | (1 << 4); /* enable for LPC ROM address range1&2, Enable 512KB rom access at 0xFFF80000 - 0xFFFFFFFF */
byte |= 1 << 6; /* enable for RTC I/O range */
pci_write_config8(dev, 0x48, byte);
pci_write_config8(dev, 0x49, 0xFF);
/* Enable 0x480-0x4bf, 0x4700-0x470B */
byte = pci_read_config8(dev, 0x4A);
byte |= ((1 << 1) + (1 << 6)); /*0x42, save the configuraion for port 0x80. */
pci_write_config8(dev, 0x4A, byte);
/* Set LPC ROM size, it has been done in sb700_lpc_init().
* enable LPC ROM range, 0xfff8: 512KB, 0xfff0: 1MB;
* enable LPC ROM range, 0xfff8: 512KB, 0xfff0: 1MB
* pci_write_config16(dev, 0x68, 0x000e)
* pci_write_config16(dev, 0x6c, 0xfff0);*/
/* Enable Tpm12_en and Tpm_legacy. I don't know what is its usage and copied from CIM. */
printk_info("Enable Tpm12_en and Tpm_legacy\n");
pci_write_config8(dev, 0x7C, 0x05);
/* P2P Bridge, BDF:0-20-4, the configuration of the registers in this dev are copied from CIM,
* TODO: I don't know what are their mean? */
printk_info("sb700_devices_por_init(): P2P Bridge, BDF:0-20-4\n");
//dev = pci_locate_device(PCI_ID(0x1002, 0x4384), 0);
dev = _pci_make_tag(0, 20, 4);
/* I don't know why CIM tried to write into a read-only reg! */
/*pci_write_config8(dev, 0x0c, 0x20) */ ;
/* Arbiter enable. */
printk_info("Arbiter enable\n");
pci_write_config8(dev, 0x43, 0xff);
/* Set PCDMA request into hight priority list. */
/* pci_write_config8(dev, 0x49, 0x1) */ ;
pci_write_config8(dev, 0x40, 0x26);
/* I don't know why CIM set reg0x1c as 0x11.
* System will block at sdram_initialize() if I set it before call sdram_initialize().
* If it is necessary to set reg0x1c as 0x11, please call this function after sdram_initialize().
* pci_write_config8(dev, 0x1c, 0x11);
* pci_write_config8(dev, 0x1d, 0x11);*/
/*CIM set this register; but I didn't find its description in RPR.
On DBM690T platform, I didn't find different between set and skip this register.
But on Filbert platform, the DEBUG message from serial port on Peanut board can't be displayed
after the bit0 of this register is set.
pci_write_config8(dev, 0x04, 0x21);
*/
printk_info("CIM set this register\n");
pci_write_config8(dev, 0x0d, 0x40);
pci_write_config8(dev, 0x1b, 0x40);
/* Enable PCIB_DUAL_EN_UP will fix potential problem with PCI cards. */
printk_info("enable pcib_dual_en_up\n");
pci_write_config8(dev, 0x50, 0x01);
#ifdef ENABLE_SATA
/* SATA Device, BDF:0-17-0, Non-Raid-5 SATA controller */
printk_info("sb700_devices_por_init(): SATA Device, BDF:0-17-0\n");
//dev = pci_locate_device(PCI_ID(0x1002, 0x4380), 0);
dev = _pci_make_tag(0, 17, 0);
/*PHY Global Control, we are using A14.
* default: 0x2c40 for ASIC revision A12 and below
* 0x2c00 for ASIC revision A13 and above.*/
printk_info("PHY Global Control\n");
pci_write_config16(dev, 0x86, 0x2C00);
#endif
}
/*
* SB700 enables all USB controllers by default in SMBUS Control.
* SB700 enables SATA by default in SMBUS Control.
*/
static void sm_init(device_t dev)
{
u8 byte;
u8 byte_old;
u8 rev;
u32 dword;
void *ioapic_base;
uint32_t power_state;
uint32_t enable_legacy_usb;
u32 nmi_option;
printk(BIOS_INFO, "sm_init().\n");
rev = get_sb700_revision(dev);
/* This works in a similar fashion to a memory resource, but without an enable bit */
ioapic_base = (void *)(pci_read_config32(dev, 0x74) & (0xffffffe0));
setup_ioapic(ioapic_base, 0); /* Don't rename IOAPIC ID. */
enable_legacy_usb = 1;
get_option(&enable_legacy_usb, "enable_legacy_usb");
/* 2.10 Interrupt Routing/Filtering */
byte = pci_read_config8(dev, 0x62);
if (enable_legacy_usb)
byte |= 0x3;
else
byte &= ~0x3;
pci_write_config8(dev, 0x62, byte);
byte = pci_read_config8(dev, 0x67);
if (enable_legacy_usb)
byte |= 0x1 << 7;
else
byte &= ~(0x1 << 7);
pci_write_config8(dev, 0x67, byte);
/* Delay back to back interrupts to the CPU. */
dword = pci_read_config16(dev, 0x64);
dword |= 1 << 13;
pci_write_config16(dev, 0x64, dword);
/* rrg:K8 INTR Enable (BIOS should set this bit after PIC initialization) */
/* rpr 2.1 Enabling Legacy Interrupt */
dword = pci_read_config8(dev, 0x62);
dword |= 1 << 2;
pci_write_config8(dev, 0x62, dword);
dword = pci_read_config32(dev, 0x78);
dword |= 1 << 9;
pci_write_config32(dev, 0x78, dword); /* enable 0xCD6 0xCD7 */
/* bit 10: MultiMediaTimerIrqEn */
dword = pci_read_config8(dev, 0x64);
dword |= 1 << 10;
pci_write_config8(dev, 0x64, dword);
/* enable serial irq */
byte = pci_read_config8(dev, 0x69);
byte |= 1 << 7; /* enable serial irq function */
byte &= ~(0xF << 2);
byte |= 4 << 2; /* set NumSerIrqBits=4 */
pci_write_config8(dev, 0x69, byte);
/* Sx State Settings
* Note: These 2 registers need to be set correctly for the S-state
* to work properly. Otherwise the system may hang during resume
* from the S-state.
*/
/*Use 8us clock for delays in the S-state resume timing sequence.*/
byte = pm_ioread(0x65);
byte &= ~(1 << 7);
pm_iowrite(0x65, byte);
/* Delay the APIC interrupt to the CPU until the system has fully resumed from the S-state. */
byte = pm_ioread(0x68);
byte |= 1 << 2;
pm_iowrite(0x68, byte);
/* IRQ0From8254 */
byte = pci_read_config8(dev, 0x41);
byte &= ~(1 << 7);
pci_write_config8(dev, 0x41, byte);
byte = pm_ioread(0x61);
if (IS_ENABLED(CONFIG_CPU_AMD_MODEL_10XXX))
byte &= ~(1 << 1); /* Clear for non-K8 CPUs */
else
byte |= 1 << 1; /* Set to enable NB/SB handshake during IOAPIC interrupt for AMD K8/K7 */
pm_iowrite(0x61, byte);
/* disable SMI */
byte = pm_ioread(0x53);
byte |= 1 << 3;
pm_iowrite(0x53, byte);
/* power after power fail */
power_state = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
get_option(&power_state, "power_on_after_fail");
if (power_state > 2) {
printk(BIOS_WARNING, "Invalid power_on_after_fail setting, using default\n");
power_state = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
}
byte = pm_ioread(0x74);
byte &= ~0x03;
if (power_state == POWER_MODE_OFF)
byte |= 0x0;
else if (power_state == POWER_MODE_ON)
byte |= 0x1;
else if (power_state == POWER_MODE_LAST)
byte |= 0x2;
byte |= 1 << 2;
pm_iowrite(0x74, byte);
printk(BIOS_INFO, "set power \"%s\" after power fail\n", power_mode_names[power_state]);
byte = pm_ioread(0x68);
byte &= ~(1 << 1);
/* 2.7 */
byte |= 1 << 2;
pm_iowrite(0x68, byte);
/* 2.7 */
byte = pm_ioread(0x65);
byte &= ~(1 << 7);
pm_iowrite(0x65, byte);
/* 2.16 */
byte = pm_ioread(0x55);
byte |= 1 << 5;
pm_iowrite(0x55, byte);
byte = pm_ioread(0xD7);
byte |= 1 << 6 | 1 << 1;
pm_iowrite(0xD7, byte);
/* 2.15 */
byte = pm_ioread(0x42);
byte &= ~(1 << 2);
pm_iowrite(0x42, byte);
/* Set up NMI on errors */
byte = inb(0x70); /* RTC70 */
byte_old = byte;
nmi_option = NMI_OFF;
get_option(&nmi_option, "nmi");
if (nmi_option) {
byte &= ~(1 << 7); /* set NMI */
printk(BIOS_INFO, "++++++++++set NMI+++++\n");
} else {
byte |= (1 << 7); /* Can not mask NMI from PCI-E and NMI_NOW */
printk(BIOS_INFO, "++++++++++no set NMI+++++\n");
}
byte &= ~(1 << 7);
if (byte != byte_old) {
outb(byte, 0x70);
}
/*rpr v2.13 2.22 SMBUS PCI Config */
byte = pci_read_config8(dev, 0xE1);
if ((REV_SB700_A11 == rev) || REV_SB700_A12 == rev) {
byte |= 1 << 0;
}
/*Set bit2 to 1, enable Io port 60h read/write SMi trapping and
*Io port 64h write Smi trapping. conflict with ps2 keyboard
*/
//byte |= 1 << 2 | 1 << 3 | 1 << 4;
byte |= 1 << 3 | 1 << 4;
pci_write_config8(dev, 0xE1, byte);
/* 2.5 Enabling Non-Posted Memory Write */
axindxc_reg(0x10, 1 << 9, 1 << 9);
/* 2.11 IO Trap Settings */
abcfg_reg(0x10090, 1 << 16, 1 << 16);
/* ab index */
pci_write_config32(dev, 0xF0, AB_INDX);
/* Initialize the real time clock */
cmos_init(0);
/* 4.3 Enabling Upstream DMA Access */
axcfg_reg(0x04, 1 << 2, 1 << 2);
/* 4.4 Enabling IDE/PCIB Prefetch for Performance Enhancement */
abcfg_reg(0x10060, 9 << 17, 9 << 17);
abcfg_reg(0x10064, 9 << 17, 9 << 17);
/* 4.5 Enabling OHCI Prefetch for Performance Enhancement, A12 */
abcfg_reg(0x80, 1 << 0, 1<< 0);
/* 4.6 B-Link Client's Credit Variable Settings for the Downstream Arbitration Equation */
/* 4.7 Enabling Additional Address Bits Checking in Downstream */
/* 4.16 IO write and SMI ordering enhancement*/
abcfg_reg(0x9c, 3 << 0, 3 << 0);
if (REV_SB700_A12 == rev) {
abcfg_reg(0x9c, 1 << 8, 1 << 8);
} else if (rev >= REV_SB700_A14) {
abcfg_reg(0x9c, 1 << 8, 0 << 8);
}
if (REV_SB700_A15 == rev) {
abcfg_reg(0x90, 1 << 21, 1 << 21);
abcfg_reg(0x9c, 1 << 5 | 1 << 9 | 1 << 15, 1 << 5 | 1 << 9 | 1 << 15);
}
/* 4.8 Set B-Link Prefetch Mode */
abcfg_reg(0x80, 3 << 17, 3 << 17);
/* 4.9 Enabling Detection of Upstream Interrupts */
abcfg_reg(0x94, 1 << 20 | 0x7FFFF, 1 << 20 | 0x00FEE);
/* 4.10: Enabling Downstream Posted Transactions to Pass Non-Posted
* Transactions for the K8 Platform (for All Revisions) */
abcfg_reg(0x10090, 1 << 8, 1 << 8);
/* Set ACPI Software clock Throttling Period to 244 us*/
byte = pm_ioread(0x68);
byte &= ~(3 << 6);
byte |= (2 << 6); /* 244us */
pm_iowrite(0x68, byte);
if (REV_SB700_A15 == rev) {
u16 word;
/* rpr v2.13 4.18 Enabling Posted Pass Non-Posted Downstream */
axindxc_reg(0x02, 1 << 9, 1 << 9);
abcfg_reg(0x9C, 0x00007CC0, 0x00007CC0);
abcfg_reg(0x1009C, 0x00000030, 0x00000030);
abcfg_reg(0x10090, 0x00001E00, 0x00001E00);
/* rpr v2.13 4.19 Enabling Posted Pass Non-Posted Upstream */
abcfg_reg(0x58, 0x0000F800, 0x0000E800);
/* rpr v2.13 4.20 64 bit Non-Posted Memory Write Support */
axindxc_reg(0x02, 1 << 10, 1 << 10);
/* rpr v2.13 2.38 Unconditional Shutdown */
byte = pci_read_config8(dev, 0x43);
byte &= ~(1 << 3);
pci_write_config8(dev, 0x43, byte);
word = pci_read_config16(dev, 0x38);
word |= 1 << 12;
pci_write_config16(dev, 0x38, word);
byte |= 1 << 3;
pci_write_config8(dev, 0x43, byte);
/* Enable southbridge MMIO decode */
dword = pci_read_config32(dev, SB_MMIO_CFG_REG);
dword &= ~(0xffffff << 8);
dword |= SB_MMIO_BASE_ADDRESS;
dword |= 0x1;
pci_write_config32(dev, SB_MMIO_CFG_REG, dword);
}
byte = pci_read_config8(dev, 0xAE);
if (IS_ENABLED(CONFIG_ENABLE_APIC_EXT_ID))
byte |= 1 << 4;
byte |= 1 << 5; /* ACPI_DISABLE_TIMER_IRQ_ENHANCEMENT_FOR_8254_TIMER */
byte |= 1 << 6; /* Enable arbiter between APIC and PIC interrupts */
pci_write_config8(dev, 0xAE, byte);
/* 4.11:Programming Cycle Delay for AB and BIF Clock Gating */
/* 4.12: Enabling AB and BIF Clock Gating */
abcfg_reg(0x10054, 0xFFFF0000, 0x1040000);
abcfg_reg(0x54, 0xFF << 16, 4 << 16);
abcfg_reg(0x54, 1 << 24, 0 << 24);
abcfg_reg(0x98, 0x0000FF00, 0x00004700);
/* 4.13:Enabling AB Int_Arbiter Enhancement (for All Revisions) */
abcfg_reg(0x10054, 0x0000FFFF, 0x07FF);
/* 4.14:Enabling Requester ID for upstream traffic. */
abcfg_reg(0x98, 1 << 16, 1 << 16);
/* 9.2: Enabling IDE Data Bus DD7 Pull Down Resistor */
byte = pm2_ioread(0xE5);
byte |= 1 << 2;
pm2_iowrite(0xE5, byte);
/* Enable IDE controller. */
byte = pm_ioread(0x59);
byte &= ~(1 << 1);
pm_iowrite(0x59, byte);
/* Enable SCI as irq9. */
outb(0x4, 0xC00);
outb(0x9, 0xC01);
printk(BIOS_INFO, "sm_init() end\n");
/* Enable NbSb virtual channel */
axcfg_reg(0x114, 0x3f << 1, 0 << 1);
axcfg_reg(0x120, 0x7f << 1, 0x7f << 1);
axcfg_reg(0x120, 7 << 24, 1 << 24);
axcfg_reg(0x120, 1 << 31, 1 << 31);
abcfg_reg(0x50, 1 << 3, 1 << 3);
}
