/* For 32-bit memory mapped registers that allow 16-bit or 32-bit access. */ bool dv_bfin_mmr_require_16_32 (struct hw *me, address_word addr, unsigned nr_bytes, bool write) { if ((addr & 0x3) == 0 && (nr_bytes == 2 || nr_bytes == 4)) return true; bfin_mmr_invalid (me, addr, nr_bytes, write, false); return false; }
bool dv_bfin_mmr_require (struct hw *me, address_word addr, unsigned nr_bytes, unsigned size, bool write) { if ((addr & 0x3) == 0 && nr_bytes == size) return true; bfin_mmr_invalid (me, addr, nr_bytes, write, false); return false; }
static bool bfin_mmr_check (struct hw *me, SIM_CPU *cpu, address_word addr, unsigned nr_bytes, bool write) { if (addr >= BFIN_CORE_MMR_BASE) { /* All Core MMRs are aligned 32bits. */ if ((addr & 3) == 0 && nr_bytes == 4) return true; } else if (addr >= BFIN_SYSTEM_MMR_BASE) { /* All System MMRs are 32bit aligned, but can be 16bits or 32bits. */ if ((addr & 0x3) == 0 && (nr_bytes == 2 || nr_bytes == 4)) return true; } else return true; /* Still here ? Must be crap. */ bfin_mmr_invalid (me, cpu, addr, nr_bytes, write); return false; }
void dv_bfin_mmr_invalid (struct hw *me, address_word addr, unsigned nr_bytes, bool write) { bfin_mmr_invalid (me, addr, nr_bytes, write, true); }