Example #1
0
u8 bfspi_read_8_bits(u16 chip_select)
{
  u16 flag_enable, flag;
  u8 ret;

  if (chip_select < 8) {
    flag = bfin_read_SPI_FLG();
    flag_enable = flag & ~(1 << (chip_select + 8));
    //PRINTK("read: flag: 0x%04x flag_enable: 0x%04x \n", flag, flag_enable);
  }
  else {
#if (defined(CONFIG_BF533) || defined(CONFIG_BF532))
    bfin_write_FIO_FLAG_C((1<<chip_select)); 
#endif
#if (defined(CONFIG_BF536) || defined(CONFIG_BF537))
        bfin_write_PORTFIO_CLEAR((1<<chip_select));
#endif
    __builtin_bfin_ssync();
  }

  /* drop SPISEL */
  bfin_write_SPI_FLG(flag_enable); 

  /* read kicks off transfer, detect end by polling RXS, we
     read the shadow register to prevent another transfer
     being started 

     While reading we write a dummy tx value, 0xff.  For
     the MMC card, a 0 bit indicates the start of a command 
     sequence therefore an all 1's sequence keeps the MMC
     card in the current state.
  */
  bfin_write_SPI_TDBR(0xff);
  bfin_read_SPI_RDBR(); __builtin_bfin_ssync();
  do { } while (!(bfin_read_SPI_STAT() & RXS)); //hardcode RXS mask
  ret = bfin_read_SPI_SHADOW(); __builtin_bfin_ssync();

  //ret = read_RDBR(); __builtin_bfin_ssync();
  PRINTK("\nkern>> read: 0x%04X\n", ret);	
  /* raise SPISEL */
  if (chip_select < 8) {
    bfin_write_SPI_FLG(flag); 
  }
  else {
#if (defined(CONFIG_BF533) || defined(CONFIG_BF532))
    bfin_write_FIO_FLAG_S((1<<chip_select)); 
#endif
#if (defined(CONFIG_BF536) || defined(CONFIG_BF537))
        bfin_write_PORTFIO_SET((1<<chip_select));
#endif
    __builtin_bfin_ssync();
  }

  return ret;
}
Example #2
0
void bfspi_write_8_bits(u16 chip_select, u8 bits)
{
  u16 flag_enable, flag;

  if (chip_select < 8) {
    flag = bfin_read_SPI_FLG();
    flag_enable = flag & ~(1 << (chip_select + 8));
    //PRINTK("kern>> chip_select: %d write: flag: 0x%04x flag_enable: 0x%04x \n", chip_select, flag, flag_enable);

    /* drop SPISEL */
    bfin_write_SPI_FLG(flag_enable); 
  }
  else {
#if (defined(CONFIG_BF533) || defined(CONFIG_BF532))
  	bfin_write_FIO_FLAG_C((1<<chip_select)); 
#endif
#if (defined(CONFIG_BF536) || defined(CONFIG_BF537))
	bfin_write_PORTFIO_CLEAR((1<<chip_select));
#endif
  	__builtin_bfin_ssync();
  }

  /* read kicks off transfer, detect end by polling RXS */
  
  bfin_write_SPI_TDBR(bits);
  bfin_read_SPI_RDBR(); __builtin_bfin_ssync();
  do {} while (!(bfin_read_SPI_STAT() & RXS)); //hardcode RXS mask
  //(void) bfin_read_SPI_SHADOW(); //discard data && clear rxs
  //__builtin_bfin_ssync();
  
  /* raise SPISEL */
  if (chip_select < 8) {
    bfin_write_SPI_FLG(flag); 
  }
  else {
#if (defined(CONFIG_BF533) || defined(CONFIG_BF532))
    bfin_write_FIO_FLAG_S((1<<chip_select)); 
#endif
#if (defined(CONFIG_BF536) || defined(CONFIG_BF537))
        bfin_write_PORTFIO_SET((1<<chip_select));
#endif
    __builtin_bfin_ssync();
  }
}
static void bf537_demux_error_irq(unsigned int int_err_irq,
				  struct irq_desc *inta_desc)
{
	int irq = 0;

#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
	if (bfin_read_EMAC_SYSTAT() & EMAC_ERR_MASK)
		irq = IRQ_MAC_ERROR;
	else
#endif
	if (bfin_read_SPORT0_STAT() & SPORT_ERR_MASK)
		irq = IRQ_SPORT0_ERROR;
	else if (bfin_read_SPORT1_STAT() & SPORT_ERR_MASK)
		irq = IRQ_SPORT1_ERROR;
	else if (bfin_read_PPI_STATUS() & PPI_ERR_MASK)
		irq = IRQ_PPI_ERROR;
	else if (bfin_read_CAN_GIF() & CAN_ERR_MASK)
		irq = IRQ_CAN_ERROR;
	else if (bfin_read_SPI_STAT() & SPI_ERR_MASK)
		irq = IRQ_SPI_ERROR;
	else if ((bfin_read_UART0_IIR() & UART_ERR_MASK) == UART_ERR_MASK)
		irq = IRQ_UART0_ERROR;
	else if ((bfin_read_UART1_IIR() & UART_ERR_MASK) == UART_ERR_MASK)
		irq = IRQ_UART1_ERROR;

	if (irq) {
		if (error_int_mask & (1L << (irq - IRQ_PPI_ERROR)))
			bfin_handle_irq(irq);
		else {

			switch (irq) {
			case IRQ_PPI_ERROR:
				bfin_write_PPI_STATUS(PPI_ERR_MASK);
				break;
#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
			case IRQ_MAC_ERROR:
				bfin_write_EMAC_SYSTAT(EMAC_ERR_MASK);
				break;
#endif
			case IRQ_SPORT0_ERROR:
				bfin_write_SPORT0_STAT(SPORT_ERR_MASK);
				break;

			case IRQ_SPORT1_ERROR:
				bfin_write_SPORT1_STAT(SPORT_ERR_MASK);
				break;

			case IRQ_CAN_ERROR:
				bfin_write_CAN_GIS(CAN_ERR_MASK);
				break;

			case IRQ_SPI_ERROR:
				bfin_write_SPI_STAT(SPI_ERR_MASK);
				break;

			default:
				break;
			}

			pr_debug("IRQ %d:"
				 " MASKED PERIPHERAL ERROR INTERRUPT ASSERTED\n",
				 irq);
		}
	} else
		pr_err("%s: IRQ ?: PERIPHERAL ERROR INTERRUPT ASSERTED BUT NO SOURCE FOUND\n",
		       __func__);

}