int platform_boot_secondary(unsigned int cpu, struct task_struct *idle) { unsigned long timeout; printk(KERN_INFO "Booting Core B.\n"); spin_lock(&boot_lock); if ((bfin_read_SYSCR() & COREB_SRAM_INIT) == 0) { /* CoreB already running, sending ipi to wakeup it */ smp_send_reschedule(cpu); } else { /* Kick CoreB, which should start execution from CORE_SRAM_BASE. */ bfin_write_SYSCR(bfin_read_SYSCR() & ~COREB_SRAM_INIT); SSYNC(); } timeout = jiffies + 1 * HZ; while (time_before(jiffies, timeout)) { if (cpu_online(cpu)) break; udelay(100); barrier(); } if (cpu_online(cpu)) { /* release the lock and let coreb run */ spin_unlock(&boot_lock); return 0; } else panic("CPU%u: processor failed to boot\n", cpu); }
static long coreb_ioctl(struct file *file, unsigned int cmd, unsigned long arg) { int ret = 0; switch (cmd) { case CMD_COREB_START: bfin_write_SYSCR(bfin_read_SYSCR() & ~0x0020); break; case CMD_COREB_STOP: bfin_write_SYSCR(bfin_read_SYSCR() | 0x0020); bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | 0x0080); break; case CMD_COREB_RESET: bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | 0x0080); break; default: ret = -EINVAL; break; } CSYNC(); return ret; }
void bfin_core1_start(void) { #ifdef BF561_FAMILY /* Enable core 1 */ bfin_write_SYSCR(bfin_read_SYSCR() & ~0x0020); #else /* Enable core 1 */ bfin_write32(RCU0_SVECT1, COREB_L1_CODE_START); bfin_write32(RCU0_CRCTL, 0); bfin_write32(RCU0_CRCTL, 0x2); /* Check if core 1 starts */ while (!(bfin_read32(RCU0_CRSTAT) & 0x2)) continue; bfin_write32(RCU0_CRCTL, 0); /* flag to notify cces core 1 application */ bfin_write32(SDU0_MSG_SET, (1 << 19)); #endif }
void native_machine_restart(char *cmd) { /* workaround reboot hang when booting from SPI */ if ((bfin_read_SYSCR() & 0x7) == 0x3) bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS); }
void native_machine_restart(char *cmd) { /* workaround reboot hang when booting from SPI */ if ((bfin_read_SYSCR() & 0x7) == 0x3) bfin_gpio_reset_spi0_ssel1(); }
void native_machine_restart(char *cmd) { if ((bfin_read_SYSCR() & 0x7) == 0x3) bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS); }
void native_machine_restart(char *cmd) { if ((bfin_read_SYSCR() & 0x7) == 0x3) bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS); //bfin_gpio_reset_spi0_ssel1();/* workaround reboot hang when booting from SPI (not used anymore) */ }